JPS57106928A - Bus controllng circuit - Google Patents

Abstract

PURPOSE:To attach and detach a data sending circuit easily by resetting and then connecting the data sending circuit to a common bus when a bus controlling circuit detects a transition from clock break to clock arrival. CONSTITUTION:When the clock detection part CDT of a bus controlling circuit BC detects a break of a clock CLK from a data sending circuit DS, the circuit DS is disconnected from a common bus CBS a constant time later under the control of a bus connection control part BSC. When the CLK is detected gain, on the other hand, a reset signal is sent from a reset signal transmission part RS to the circuit DS, which is connected to the CBS a fixed time later. Therfore, the disconnection from the CBS is made automatically in the power break of the circuit DS or card extraction, and when the card is inserted after the power source is turned on or after a maintenace check is made, the circuit DS is reset in its initial state and then connected automatically to the CBS, thus connecting and disconnecting the circuit DS without exerting an evil influence upon the CBS.