JPS57106928A - Bus controllng circuit - Google Patents

Bus controllng circuit

Info

Publication number
JPS57106928A
JPS57106928A JP55182572A JP18257280A JPS57106928A JP S57106928 A JPS57106928 A JP S57106928A JP 55182572 A JP55182572 A JP 55182572A JP 18257280 A JP18257280 A JP 18257280A JP S57106928 A JPS57106928 A JP S57106928A
Authority
JP
Japan
Prior art keywords
circuit
cbs
bus
ds
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55182572A
Inventor
Hisao Kono
Eiji Minamitani
Shunichi Naito
Yuji Shibata
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55182572A priority Critical patent/JPS57106928A/en
Publication of JPS57106928A publication Critical patent/JPS57106928A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring

Abstract

PURPOSE:To attach and detach a data sending circuit easily by resetting and then connecting the data sending circuit to a common bus when a bus controlling circuit detects a transition from clock break to clock arrival. CONSTITUTION:When the clock detection part CDT of a bus controlling circuit BC detects a break of a clock CLK from a data sending circuit DS, the circuit DS is disconnected from a common bus CBS a constant time later under the control of a bus connection control part BSC. When the CLK is detected gain, on the other hand, a reset signal is sent from a reset signal transmission part RS to the circuit DS, which is connected to the CBS a fixed time later. Therfore, the disconnection from the CBS is made automatically in the power break of the circuit DS or card extraction, and when the card is inserted after the power source is turned on or after a maintenace check is made, the circuit DS is reset in its initial state and then connected automatically to the CBS, thus connecting and disconnecting the circuit DS without exerting an evil influence upon the CBS.
JP55182572A 1980-12-23 1980-12-23 Bus controllng circuit Pending JPS57106928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55182572A JPS57106928A (en) 1980-12-23 1980-12-23 Bus controllng circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182572A JPS57106928A (en) 1980-12-23 1980-12-23 Bus controllng circuit

Publications (1)

Publication Number Publication Date
JPS57106928A true JPS57106928A (en) 1982-07-03

Family

ID=16120615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182572A Pending JPS57106928A (en) 1980-12-23 1980-12-23 Bus controllng circuit

Country Status (1)

Country Link
JP (1) JPS57106928A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5964855A (en) * 1997-04-07 1999-10-12 International Business Machines Corporation Method and system for enabling nondisruptive live insertion and removal of feature cards in a computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5964855A (en) * 1997-04-07 1999-10-12 International Business Machines Corporation Method and system for enabling nondisruptive live insertion and removal of feature cards in a computer system

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