JPS57105032A - Queue loading control system of signal processing device - Google Patents

Queue loading control system of signal processing device

Info

Publication number
JPS57105032A
JPS57105032A JP55182516A JP18251680A JPS57105032A JP S57105032 A JPS57105032 A JP S57105032A JP 55182516 A JP55182516 A JP 55182516A JP 18251680 A JP18251680 A JP 18251680A JP S57105032 A JPS57105032 A JP S57105032A
Authority
JP
Japan
Prior art keywords
queue
circuit
selecting
circuits
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55182516A
Other languages
Japanese (ja)
Inventor
Koichi Shimomukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55182516A priority Critical patent/JPS57105032A/en
Publication of JPS57105032A publication Critical patent/JPS57105032A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To freely combine a circuit attribute of a circuit in a signal receiving device, and also to inhibit loading of an unnecessary data onto a queue device, by providing a queue selecting and designating circuit and a queue collating circuit on each queue device. CONSTITUTION:On queue devices 50-5n, queue selecting and designating circuits 30-3n and queue collating circuits 40-4n are provided. At first, when queue selecting information is written in each circuit 30-3n from a processing device 10, the circuits 30-3n send out a queue selecting output to the corresponding circuits 40-4n, respectively. In this state, if the circuit state is varied, an output from a signal receiving device 20 is outputted to the circuits 40-4n, is compared with the queue selecting output, and in case of coincidence, the queue selecting information is supplied to the queue devices 50-5n. In this case, the device 20 outputs report information to gate terminals F0-Fn from its output terminal, and loads the report information onto the queue devices 50-5n selected by a queue selecting signal.
JP55182516A 1980-12-23 1980-12-23 Queue loading control system of signal processing device Pending JPS57105032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55182516A JPS57105032A (en) 1980-12-23 1980-12-23 Queue loading control system of signal processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182516A JPS57105032A (en) 1980-12-23 1980-12-23 Queue loading control system of signal processing device

Publications (1)

Publication Number Publication Date
JPS57105032A true JPS57105032A (en) 1982-06-30

Family

ID=16119659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182516A Pending JPS57105032A (en) 1980-12-23 1980-12-23 Queue loading control system of signal processing device

Country Status (1)

Country Link
JP (1) JPS57105032A (en)

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