JPS57103435A - Fm receiver - Google Patents

Fm receiver

Info

Publication number
JPS57103435A
JPS57103435A JP17901980A JP17901980A JPS57103435A JP S57103435 A JPS57103435 A JP S57103435A JP 17901980 A JP17901980 A JP 17901980A JP 17901980 A JP17901980 A JP 17901980A JP S57103435 A JPS57103435 A JP S57103435A
Authority
JP
Japan
Prior art keywords
frequency
multipath distortion
ram32
stored
delay time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17901980A
Other languages
Japanese (ja)
Inventor
Toshifumi Shibuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17901980A priority Critical patent/JPS57103435A/en
Publication of JPS57103435A publication Critical patent/JPS57103435A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/10Means associated with receiver for limiting or suppressing noise or interference

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)

Abstract

PURPOSE:To reduce the multipath distortion with a simple operation, by storing a delay time of the variable delay equipment, which is used in a multipath distortion reducing circuit, in a storage device in correspondence to a receiving frequency. CONSTITUTION:A frequency division ratio N of a programmable frequency divider 2 of a local oscillator 102 of the PLL constitution of an FM receiver is stored in an RAM32 of a control device 103. A frequency division ratio M of a programmable frequency divider 43, which determines a delay time adapted to a receiving frequency, of a CCD variable delay equipment 105 for reduction of multipath distortion is stored in the RAM32. In case of channel selection of a broadcast station, an operating device 31 of the device 103 is controlled by the key operation of a keyboard 34 to read division ratios N and M stored in the RAM32, and division ratios N and M are set to respective frequency dividers 24 and 43 of the local oscillator 102 and the control device 103. Then, a channel is selected, and a delay time of the delay equipment 105 adapted to the station is selected, thus reducing the multipath distortion with a simple operation.
JP17901980A 1980-12-19 1980-12-19 Fm receiver Pending JPS57103435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17901980A JPS57103435A (en) 1980-12-19 1980-12-19 Fm receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17901980A JPS57103435A (en) 1980-12-19 1980-12-19 Fm receiver

Publications (1)

Publication Number Publication Date
JPS57103435A true JPS57103435A (en) 1982-06-28

Family

ID=16058682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17901980A Pending JPS57103435A (en) 1980-12-19 1980-12-19 Fm receiver

Country Status (1)

Country Link
JP (1) JPS57103435A (en)

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