JPS57103194A - Erasing circuit for nonvolatile memory contents - Google Patents

Erasing circuit for nonvolatile memory contents

Info

Publication number
JPS57103194A
JPS57103194A JP17926180A JP17926180A JPS57103194A JP S57103194 A JPS57103194 A JP S57103194A JP 17926180 A JP17926180 A JP 17926180A JP 17926180 A JP17926180 A JP 17926180A JP S57103194 A JPS57103194 A JP S57103194A
Authority
JP
Japan
Prior art keywords
nonvolatile memory
switch
gate circuits
contents
nonlock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17926180A
Other languages
Japanese (ja)
Other versions
JPS595998B2 (en
Inventor
Shintaro Yamamoto
Toshiaki Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chino Works Ltd
Original Assignee
Chino Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chino Works Ltd filed Critical Chino Works Ltd
Priority to JP55179261A priority Critical patent/JPS595998B2/en
Publication of JPS57103194A publication Critical patent/JPS57103194A/en
Publication of JPS595998B2 publication Critical patent/JPS595998B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

PURPOSE:To eliminate erroneous erasure with simple constitution by using one nonlock switch and two gate circuits, and by erasing the contents of a nonvolatile memory by a CPU only when the nonlock switch is pushed for a prescribed time. CONSTITUTION:A nonlock switch 1 for erasing the contents of a nonvolatile memory 4 and gate circuits 21 and 22 which output signals showing different states according to the state of the switch 1 are provided. Then, a CPU3 sends a clock signal repeatedly at prescribed cycles to gate circuits 21 and 22 to fetch signals from the gate circuits 21 and 22 and when the on state of the switch 1 continues for a prescribed time, the contents of the nonvolatile memory 4 are erased.
JP55179261A 1980-12-17 1980-12-17 Non-volatile memory content erasing circuit Expired JPS595998B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55179261A JPS595998B2 (en) 1980-12-17 1980-12-17 Non-volatile memory content erasing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55179261A JPS595998B2 (en) 1980-12-17 1980-12-17 Non-volatile memory content erasing circuit

Publications (2)

Publication Number Publication Date
JPS57103194A true JPS57103194A (en) 1982-06-26
JPS595998B2 JPS595998B2 (en) 1984-02-08

Family

ID=16062751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55179261A Expired JPS595998B2 (en) 1980-12-17 1980-12-17 Non-volatile memory content erasing circuit

Country Status (1)

Country Link
JP (1) JPS595998B2 (en)

Also Published As

Publication number Publication date
JPS595998B2 (en) 1984-02-08

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