JPS5698091A - Multi-frequency signal receiver - Google Patents

Multi-frequency signal receiver

Info

Publication number
JPS5698091A
JPS5698091A JP79280A JP79280A JPS5698091A JP S5698091 A JPS5698091 A JP S5698091A JP 79280 A JP79280 A JP 79280A JP 79280 A JP79280 A JP 79280A JP S5698091 A JPS5698091 A JP S5698091A
Authority
JP
Japan
Prior art keywords
circuit
level
frequency signal
reception signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP79280A
Other languages
Japanese (ja)
Other versions
JPS5920225B2 (en
Inventor
Kazunari Hirano
Masanori Nakamura
Yasumasa Iwase
Yoshikatsu Shiraishi
Kazuhiko Takaoka
Yujiro Sasahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP55000792A priority Critical patent/JPS5920225B2/en
Publication of JPS5698091A publication Critical patent/JPS5698091A/en
Publication of JPS5920225B2 publication Critical patent/JPS5920225B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/18—Electrical details
    • H04Q1/30—Signalling arrangements; Manipulation of signalling currents
    • H04Q1/44—Signalling arrangements; Manipulation of signalling currents using alternate current
    • H04Q1/444—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
    • H04Q1/45—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling
    • H04Q1/453—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling in which m-out-of-n signalling frequencies are transmitted

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To eliminate the disturbing noise, by identifying whether the level of the reception signal is within a range of prescribed stepped level, transmitting the output after the reception signal was comfirmed offective as the multi-frequency signal and then excerising a level control only over the undesired circuit noise. CONSTITUTION:The level identifying circuit 9 indentifies whether the level of the reception signal supplied to the buffer amplifier 1 is within a prescribed stepped level range. The logic circuit 12 supplies the reception signal via the low-group identifying circuit 6 and the high-group identifying circuit 10 and transmits the output when approving the effectiveness of the received signal as the multi-frequency signal. Then the level range identified by the comparators C1-C4 is stored in the momories M1-M4 each of the circuit 9 at the moment when the output is transmitted from the circuit 12. At the same time, the rear edge of the received multi-frequency signal is detected by the mono-multi 15, and the memories M1-M4 are reset after a fixed time. Then the variable attenuator circuit 4 is controlled via the relays R1-R4 and in accordance with the state of the memories M1-M4 to perform the level control. Thus the disturbance noise can be eliminated.
JP55000792A 1980-01-08 1980-01-08 multifrequency signal receiver Expired JPS5920225B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55000792A JPS5920225B2 (en) 1980-01-08 1980-01-08 multifrequency signal receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55000792A JPS5920225B2 (en) 1980-01-08 1980-01-08 multifrequency signal receiver

Publications (2)

Publication Number Publication Date
JPS5698091A true JPS5698091A (en) 1981-08-07
JPS5920225B2 JPS5920225B2 (en) 1984-05-11

Family

ID=11483529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55000792A Expired JPS5920225B2 (en) 1980-01-08 1980-01-08 multifrequency signal receiver

Country Status (1)

Country Link
JP (1) JPS5920225B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6471261A (en) * 1987-09-11 1989-03-16 Nec Corp Multi-frequency signal receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6471261A (en) * 1987-09-11 1989-03-16 Nec Corp Multi-frequency signal receiver

Also Published As

Publication number Publication date
JPS5920225B2 (en) 1984-05-11

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