JPS5694A - Programmable memory unit and programming method - Google Patents

Programmable memory unit and programming method

Info

Publication number
JPS5694A
JPS5694A JP6079380A JP6079380A JPS5694A JP S5694 A JPS5694 A JP S5694A JP 6079380 A JP6079380 A JP 6079380A JP 6079380 A JP6079380 A JP 6079380A JP S5694 A JPS5694 A JP S5694A
Authority
JP
Japan
Prior art keywords
memory unit
programmable memory
programming method
programming
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6079380A
Other languages
Japanese (ja)
Inventor
Jiyon Patsuchi Richiyaado
Danieru Roozu Jiyunia Jiyooji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of JPS5694A publication Critical patent/JPS5694A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233Integrated injection logic structures [I2L]
    • H01L27/0244I2L structures integrated in combination with analog structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
JP6079380A 1979-05-10 1980-05-09 Programmable memory unit and programming method Pending JPS5694A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US3777079A 1979-05-10 1979-05-10

Publications (1)

Publication Number Publication Date
JPS5694A true JPS5694A (en) 1981-01-06

Family

ID=21896235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6079380A Pending JPS5694A (en) 1979-05-10 1980-05-09 Programmable memory unit and programming method

Country Status (4)

Country Link
JP (1) JPS5694A (en)
DE (1) DE3017636A1 (en)
FR (1) FR2456369A1 (en)
GB (1) GB2052905B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764800A (en) * 1986-05-07 1988-08-16 Advanced Micro Devices, Inc. Seal structure for an integrated circuit
KR0149259B1 (en) * 1995-06-30 1998-10-15 김광호 Fuse signature device for semiconductor memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE755039A (en) * 1969-09-15 1971-02-01 Ibm PERMANENT SEMI-CONDUCTOR MEMORY
US3810127A (en) * 1970-06-23 1974-05-07 Intel Corp Programmable circuit {13 {11 the method of programming thereof and the devices so programmed
US3848238A (en) * 1970-07-13 1974-11-12 Intersil Inc Double junction read only memory
FR2334170A1 (en) * 1975-12-05 1977-07-01 Honeywell Bull Soc Ind DEAD MEMORY BUILT-IN
US4152627A (en) * 1977-06-10 1979-05-01 Monolithic Memories Inc. Low power write-once, read-only memory array

Also Published As

Publication number Publication date
GB2052905B (en) 1983-11-09
FR2456369A1 (en) 1980-12-05
DE3017636A1 (en) 1980-11-20
GB2052905A (en) 1981-01-28

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