GB2052905A - Improved memory device - Google Patents
Improved memory device Download PDFInfo
- Publication number
- GB2052905A GB2052905A GB8015459A GB8015459A GB2052905A GB 2052905 A GB2052905 A GB 2052905A GB 8015459 A GB8015459 A GB 8015459A GB 8015459 A GB8015459 A GB 8015459A GB 2052905 A GB2052905 A GB 2052905A
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory device
- diode
- common
- programmable memory
- programming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims 1
- 238000002347 injection Methods 0.000 abstract description 15
- 239000007924 injection Substances 0.000 abstract description 15
- 239000007787 solid Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 9
- 230000015654 memory Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A memory device is provided for an integrated injection logic (I<2>L) device in solid state form by a resistor (11) connected at one end to the logic device (12, 18, 19, 20), and a diode (13, 14), having its cathode connected to the other end of the resistor (11) at a programming junction (48), and its anode connected to a common point (41). If the diode conductors are melted or deformed by reverse diode current from the programming junction to the common point, a low impedance path is formed, and the logic portion is provided with a first logic input. If the diode conductors are left unmelted or intact, the logic portion is provided with a second logic input. The diodes and logic transistor base-emitter junctions are poled for easy flow in the same loop sense. <IMAGE>
Description
SPECIFICATION
Improved memory device
This invention relates to a memory device, and particularly to a memory device for an integrated injection logic (12L) device, and a method for programming such a memory device.
Memory devices of the permanent type which can be programmed in the field (as contrasted with a manufacturing plant) are sometimes referred to as programmable read only memories (PROM). One such PROM device uses a resistance lead or element which is opened by an electric current to provide the desired programming input condition. However, such an opening leaves debris or random paths which introduce leakage that is undesirable or unacceptable, particularly in 12L circuits. Another such PROM device uses electrically programmable MOS devices. However those devices require or operate with a relatively large voltage, for example 5 volts. In many applications, a single cell battery with a nominal voltage of about 1.5 volts must be used, so that those electrically programmable
PROM devices cannot be used.In such low voltage applications, 12L devices can be employed. Thus, there is a need for 12L programmable memory devices. If those devices must be programmed at a manufacturing plant where manufacturing techniques are available, an inventory of all possible programmed memories must be kept on hand (a relatively wasteful condition). Or, each memory must be programmed in response to a specific request (a condition that may be slow if there is a backlog of requests).
The l2L memory device provided by the invention can be easily programmed by almost anyone with relatively simple apparatus.
The integrated injection logic memory device of the invention has a single arrangement for mass production, and can be easily programmed with relatively simple equipment at the location, by the user, if need be, where the desired memory information becomes known or determined.
Thus, the integrated injection logic memory device of the invention can be easily and permanently electrically programmed by existing and changing circuit conditions.
Briefly, the invention utilizes one or more integrated injection logic memory devices each having a resistor and programmable diode connected to the respective integrated injection logic device input. The diode has its cathode connected to the resistor at a programming junction, and its anode connected to a point of reference potential or ground. If a diode is left intact or unmodified, one logic condition is presented to its respective integrated injection logic device input. However, if the diode junction and leads are modified or melted by applying a suitable voltage and current to the programming junction of the diode and the resistor, current flows in the reverse direction through the diode to melt the diode junction and leads and effectively ground the resistor. This provides a second logic condition to its respective integrated injection logic device input.The resistor is provided to prevent excessive current from flowing into the logic device input. Thus, it is relatively simple to program each memory device in accordance with any desired condition or arrangement. Such programming can be done by relatively unskilled people with relatively simple equipment, so that our improved memory device provides a single versatile structure that can be programmed to suit any need.
The structure and operation of the invention, may be better understood from the following description given in connection with the accompanying drawing, in which:
Figure 1 shows a top plan view of one memory device in accordance with the invention and its associated logic circuit, Fig. 1 being taken along the line 1-1 in Fig. 2;
Figure 2 shows a cross-sectional view of the memory device and logic circuit taken along the line 2-2 in Fig. 1; and
Figure 3 shows an equivalent circuit diagram of our memory device and logic circuit of Figs. 1 and 2.
Figs. 1 and 2, show a top plan view and a cross-sectional view respectively of the memory device and the logic circuit associated with it. While these figures are not shown to any relative scale as far as an actual device is concerned, the figures are correspondingly positioned. These figures, show only one logic circuit, and only one programmable memory device in accordance with the invention. However, it is to be understood that a plurality of such logic circuits and of such programmable memory devices would normally be provided.
The memory invention and the logic circuit are provided in integrated injection logic (12L) form. Such a form normally includes a substrate 10 which provides support and insulation, and which may be made of any suitable material such as silicon. A buried layer 11 of
N + type material such as arsenic doped silicon is formed on the substrate 10, and an epitaxial or epi-layer 12 of N type material is grown on the substrate 10 and the buried layer 11.
The integrated injection logic device includes a region 21 of P type material such as boron doped silicon. This material is diffused or implanted into the epi-layer 12. Another region 18 of P type material is provided in the epi-layer 12, and two or more regions 19, 20 of N + type material are provided in the region 18, all as shown in the right hand portions of Figs. 1 and 2. In addition, a region 22 of N + type material is provided from the upper surface to the buried layer 11 to provide a ground for the logic device. The various regions at the upper surface are provided with a suitable layer 40 of insulating material such as silicon dioxide, and the particular regions 22, 21, 20, 19, 18 are respectively provided with external metallic leads or terminals 47, 46, 45, 44, 43. These termi nals may be aluminum.They are shown in phantom in Fig. 1 in the interest of clarity.
As shown by the equivalent circuit in Fig.
3, the P region 21, the N epi-layer 12, and the P region 18 form the emitter, base, and collector respectively of a horizontal PNP type injection transistor. The N + regions 19, 20, the P region 18, and the N epi-layer 12 form the collectors, base, and emitter respectively of a vertical logic transistor. The P region 18 is thus common to both transistors. The terminal 46 would be connected to a suitable current source, and the collectors 44, 45 would be connected to suitable output circuits, which may be included in the same structure shown, or in an external structure. The structure described thus far forms a known integrated injection logic device whose input would be connected to the base terminal 43 of the vertical transistor, and whose output would be provided at the collector terminals 44, 45 of the vertical transistor.
In order to provide a programmable memory for the logic device described, a resistor and diode are connected to the logic transistor as shown schematically in Fig. 3. As shown in
Figs. 1 and 2, the resistor is provided in a wall of P type isolation material 30 extending from the upper surface to the substrate 10, and enclosing the N epilayer 1 2 and the N + buried layer 11. The resistor itself is formed by two P regions 15, 16 and a connecting P region 17. These P regions may be diffused or implanted. The terminal 43 connects the P region 16 to the P region 18. The anode of the diode is provided by a P region 13 in the
N N epi-layer 12, and the cathode is provided by an N + region 14 in the P region 13. A metallic lead 42 connects the N + region 14 (or diode cathode) to the P region 15 of the resistor.A programming or logic input terminal 48 is connected to the lead 42. A lead or terminal 41 is connected to the P region 13 forming the diode anode. These leads may also be aluminum. The terminal 41 would be connected to ground or a point of reference potential. Thus as shown in Fig. 3, a resistor has one end connected to the base 18 of the logic transistor. The other end of the resistor is connected by a lead or conductor 42 to the diode cathode formed by the N + region 14.
The diode anode formed by the P region 13 is connected to ground or a point of reference potential. Thus the forward direction of conduction in the diode is from ground to the terminal 42.
If the formed diode is left intact, and if no signal is applied to the programming or logic input terminal 48, the base 1 8 of the logic transistor is floating. When supplied with an injector input current, the injector transistor causes the logic transistor to conduct from its collectors to its emitter. This provides one logic condition. However, if the diode is modified so as to ground the programming or logic input terminal 48, the base 18 of the logic transistor is grounded so that it does not conduct. Hence, another logic condition is provided at the collectors of the logic transistor.
The diode can be programmed by a programming generator 50 that provides a suitable programming input of predetermined voltage and current in the reverse direction through the diode for a predetermined time.
This programming input is supplied to the terminal 48 as a positive voltage with respect to ground. When this input is applied, the formed resistor (which may be in the order of 1,000 to 10,000 ohms) does not permit much current to flow toward the logic transistor. Consequently, the programming current flows primarily in the reverse direction through the formed diode. This current causes the diode to heat and melt the conductors 41, 42 connected to N + region 14 and the P region 13. The electric field that is present causes the melted conductors 41, 42 to flow through the softened regions 13, 14 and form a metallic path across or through those regions 13, 14. When the melted conductors 41, 42 cool and solidify, they form essentially a short circuit or very low impedance path (less than 1 ohm) between the terminals 41, 42.If the terminal 41 is grounded, this ground appears at the base of the logic transistor to supply the desired logic condition that is opposite to the floating condition if no ground is provided.
Note that the poling of the base-emitter path of the logic transistor is such that the current flowing through this junction during the application of the positive programming pulse is in the direction of easy flow and is limited by the resistor 17, so that relatively little energy is dissipated at this junction. On the other hand, the formed diode 13, 14 is poled in the contrary sense with respect to the programming impulse and there is no current limiting resistor, so that a maximum of energy is dissipated at the junction presented by the formed diode 13, 14, with resultant maximum heating effect, to produce the desired fusion.
What has been described and shown above in connection with Figs. 1, 2 and 3 constitutes a single programmable element. Any number of these elements can be formed on a substrate of any desired size to form a complete PROM array with any number of programmable units. The device and method herein described make it possible to easily program one or more devices of the array, as desired, so that the desired PROM outputs will be obtained. The programming is provided or accomplished with relatively simple equipment, namely a programming generator that supplies the desired current for the desired length of time. For one diode having a reverse breakdown voltage of 5 volts, this programming was provided with a constant current of 300 milliamperes for 3 milliseconds.The programming generator can be connected to each terminal 48 which is to provide the desired memory condition for its respective logic transistor. Other terminals can be selectively left unprogrammed. These unprogrammed terminals may be electrically programmed by logic signals if desired under various operating conditions. Thus, one standard arrangement of any number of integrated injection logic devices, each with a programming device, can be programmed as desired in accordance with the invention. The programming device and method are relatively simple, and permit almost anyone to do this programming in the field (i.e. away from the manufacturing plant), thus increasing the uses and versatility of integrated injection logic devices.
Persons skilled in the art will appreciate the many modifications that may be made. For example, the integrated injection logic devices may take a variety of different forms, depending upon the exact manufacturing conditions and preferences. And, any number of these devices may be programmed in accordance with the invention, by almost any type of programming generator that supplies the proper voltage and current for the desired duration. The programmable diodes may be connected with their anodes connected to the resistors and their cathodes connected to ground if the forward voltage drop of the diodes is sufficiently high so as not to ground the base of the logic transistor. If that forward voltage drop is insufficient, two or more diodes can be connected in series. Such diodes would also be programmed with current in the reverse direction. However, it is preferable that the diodes be connected as shown in the drawing, since that arrangement is more reliable. While the invention has been described with reference to a particular embodiment, it is to be understood that modifications may be made without departing from the spirit thereof.
Claims (12)
1. A programmable memory device having a plurality of output circuits characterized in that each of said output circuits is individually connected -with a corresponding separate diode through a corresponding separate resistor, and an individual programming connection is respectively electrically associated with each resistor to diode junction.
2. A programmable memory device according to Claim 1 characterized in that said diodes are formed in a common integrated circuit structure on a common base.
3. A programmable memory device according to Claim 1 or 2 characterized in that said resistors are formed in a common integrated circuit structure on a common base.
4. A programmable memory device according to Claim 1 characterized in that said diodes and said resistors are formed in a common integrated circuit structure on a common base.
5. A programmable memory device according to Claim 1 characterized in that said output circuits comprise transistor circuits formed in a common integrated circuit with said resistors and said diodes on a common base.
6. A programmable memory device according to Claim 5 characterized in that isolating barrier situated within said integrated structure surrounds end resistor element.
7. A programmable memory device according to any one of the foregoing claims characterized in that the diode terminals remote from the programming connection are connected with a common electric connection.
8. A programmable memory device according to Claim 7 characterized in that all of said diodes are connected between said programming connection and said common electrical connection with the same poling sense.
9. A programmable memory device according to Claim 5 characterized in that each of said resistors is connected with the baseemitter path of its corresponding transistor, that the ends of said diodes remote from said programming connections are connected with a a common electrical connection which is also common with said emitters and that the diodes and base-emitter junctions situated in a common loop are poled with coincident directions of easy flow.
10. A programmable memory device according to Claim 9 characterized in that said integrated circuit structure comprises a common support on which there is situated on
N + layer, over which there is situated an Ntype layer and the diode, transistor and resistor elements are embedded in said N-type layer.
11. A method of programming individual logic circuits formed on an N + type buried layer, each of said logic circuits being connected to an external programming terminal through a respective resistor, and each external programming terminal being connected to a point of reference potential through a re spective cathode-anode path of a diode device, comprising the steps of:
a. sequentially connecting a generator capable of producing a selected current for a selected time duration to selected ones of said external programming terminals;
b. and operating said generator when connected to each selected terminal to cause current to flow in the cathode to anode direction in said diode device and melt portions of the conductors of said diode device to provide a low resistance path from the respective programming terminal to said point of reference potential.
12. A programmable memory device substantially as described herein with reference to Figs. 1, 2 and 3 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US3777079A | 1979-05-10 | 1979-05-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2052905A true GB2052905A (en) | 1981-01-28 |
| GB2052905B GB2052905B (en) | 1983-11-09 |
Family
ID=21896235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8015459A Expired GB2052905B (en) | 1979-05-10 | 1980-05-09 | Memory device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5694A (en) |
| DE (1) | DE3017636A1 (en) |
| FR (1) | FR2456369A1 (en) |
| GB (1) | GB2052905B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2302953A (en) * | 1995-06-30 | 1997-02-05 | Samsung Electronics Co Ltd | Semiconductor fuse circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4764800A (en) * | 1986-05-07 | 1988-08-16 | Advanced Micro Devices, Inc. | Seal structure for an integrated circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BE755039A (en) * | 1969-09-15 | 1971-02-01 | Ibm | PERMANENT SEMI-CONDUCTOR MEMORY |
| US3810127A (en) * | 1970-06-23 | 1974-05-07 | Intel Corp | Programmable circuit {13 {11 the method of programming thereof and the devices so programmed |
| US3848238A (en) * | 1970-07-13 | 1974-11-12 | Intersil Inc | Double junction read only memory |
| FR2334170A1 (en) * | 1975-12-05 | 1977-07-01 | Honeywell Bull Soc Ind | DEAD MEMORY BUILT-IN |
| US4152627A (en) * | 1977-06-10 | 1979-05-01 | Monolithic Memories Inc. | Low power write-once, read-only memory array |
-
1980
- 1980-05-08 DE DE19803017636 patent/DE3017636A1/en not_active Withdrawn
- 1980-05-09 FR FR8010399A patent/FR2456369A1/en active Pending
- 1980-05-09 JP JP6079380A patent/JPS5694A/en active Pending
- 1980-05-09 GB GB8015459A patent/GB2052905B/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2302953A (en) * | 1995-06-30 | 1997-02-05 | Samsung Electronics Co Ltd | Semiconductor fuse circuit |
| GB2302953B (en) * | 1995-06-30 | 1998-02-04 | Samsung Electronics Co Ltd | Semiconductor fuse circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5694A (en) | 1981-01-06 |
| GB2052905B (en) | 1983-11-09 |
| FR2456369A1 (en) | 1980-12-05 |
| DE3017636A1 (en) | 1980-11-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |