FR2456369A1 - PROGRAMMABLE MEMORY AND PROGRAMMING METHOD - Google Patents

PROGRAMMABLE MEMORY AND PROGRAMMING METHOD

Info

Publication number
FR2456369A1
FR2456369A1 FR8010399A FR8010399A FR2456369A1 FR 2456369 A1 FR2456369 A1 FR 2456369A1 FR 8010399 A FR8010399 A FR 8010399A FR 8010399 A FR8010399 A FR 8010399A FR 2456369 A1 FR2456369 A1 FR 2456369A1
Authority
FR
France
Prior art keywords
programmable memory
programming method
resistor
corresponding separate
diode13
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR8010399A
Other languages
French (fr)
Inventor
Richard John Patch
George Daniel Rose Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of FR2456369A1 publication Critical patent/FR2456369A1/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H01L27/0244—I2L structures integrated in combination with analog structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

MEMOIRE AISEMENT PROGRAMMABLE SUR LE LIEU DE L'UTILISATION. ELLE COMPREND PLUSIEURS CIRCUITS DE SORTIE12, 18, 19, 20, 21 REUNIS CHACUN A UNE DIODE SEPAREE CORRESPONDANTE13, 14 PAR L'INTERMEDIAIRE D'UNE RESISTANCE SEPAREE CORRESPONDANTE 17 ET EN CE QU'UNE CONNEXION INDIVIDUELLE DE PROGRAMMATION 48 EST ELECTRIQUEMENT ASSOCIEE RESPECTIVEMENT A CHAQUE JONCTION42 RESISTANCE-DIODE. APPLICATION AUX DISPOSITIFS A LOGIQUE A INJECTION INTEGREE.EASY PROGRAMMABLE MEMORY AT THE LOCATION OF USE. IT INCLUDES SEVERAL OUTPUT CIRCUITS12, 18, 19, 20, 21 EACH ASSOCIATED WITH A CORRESPONDING SEPARATE DIODE13, 14 THROUGH A CORRESPONDING SEPARATE RESISTOR 17 AND AS AN INDIVIDUAL PROGRAMMING CONNECTION 48 IS RESPECTIVELY ASSOCIATED WITH RESPECTING EACH JUNCTION 42 RESISTOR-DIODE. APPLICATION TO INTEGRATED INJECTION LOGIC DEVICES.

FR8010399A 1979-05-10 1980-05-09 PROGRAMMABLE MEMORY AND PROGRAMMING METHOD Pending FR2456369A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US3777079A 1979-05-10 1979-05-10

Publications (1)

Publication Number Publication Date
FR2456369A1 true FR2456369A1 (en) 1980-12-05

Family

ID=21896235

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8010399A Pending FR2456369A1 (en) 1979-05-10 1980-05-09 PROGRAMMABLE MEMORY AND PROGRAMMING METHOD

Country Status (4)

Country Link
JP (1) JPS5694A (en)
DE (1) DE3017636A1 (en)
FR (1) FR2456369A1 (en)
GB (1) GB2052905B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0245014A2 (en) * 1986-05-07 1987-11-11 Advanced Micro Devices, Inc. Seal structure for an integrated circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0149259B1 (en) * 1995-06-30 1998-10-15 김광호 Fuse signature device for semiconductor memory

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3641516A (en) * 1969-09-15 1972-02-08 Ibm Write once read only store semiconductor memory
US3810127A (en) * 1970-06-23 1974-05-07 Intel Corp Programmable circuit {13 {11 the method of programming thereof and the devices so programmed
US3848238A (en) * 1970-07-13 1974-11-12 Intersil Inc Double junction read only memory
FR2334170A1 (en) * 1975-12-05 1977-07-01 Honeywell Bull Soc Ind DEAD MEMORY BUILT-IN
US4152627A (en) * 1977-06-10 1979-05-01 Monolithic Memories Inc. Low power write-once, read-only memory array

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3641516A (en) * 1969-09-15 1972-02-08 Ibm Write once read only store semiconductor memory
US3810127A (en) * 1970-06-23 1974-05-07 Intel Corp Programmable circuit {13 {11 the method of programming thereof and the devices so programmed
US3848238A (en) * 1970-07-13 1974-11-12 Intersil Inc Double junction read only memory
FR2334170A1 (en) * 1975-12-05 1977-07-01 Honeywell Bull Soc Ind DEAD MEMORY BUILT-IN
US4152627A (en) * 1977-06-10 1979-05-01 Monolithic Memories Inc. Low power write-once, read-only memory array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0245014A2 (en) * 1986-05-07 1987-11-11 Advanced Micro Devices, Inc. Seal structure for an integrated circuit
EP0245014A3 (en) * 1986-05-07 1989-07-12 Advanced Micro Devices, Inc. Seal structure for an integrated circuit

Also Published As

Publication number Publication date
GB2052905A (en) 1981-01-28
JPS5694A (en) 1981-01-06
DE3017636A1 (en) 1980-11-20
GB2052905B (en) 1983-11-09

Similar Documents

Publication Publication Date Title
DE68919118D1 (en) Programmable logic device with programmable word line connections.
FR1515767A (en) Device automatically correcting the distribution in four-stroke engines
DE3587704T2 (en) Photoconductive device with perylene dyes.
FR2519177B1 (en) DEVICE WITH INTEGRATED DYNAMIC RAM MEMORY CIRCUITS
DE68919404D1 (en) Semiconductor memory with serial input / serial output.
FR2456369A1 (en) PROGRAMMABLE MEMORY AND PROGRAMMING METHOD
FR2694121B1 (en) MEMORY IN INTEGRATED CIRCUIT WITH PRELOADING PRIOR TO OUTPUT.
DE68905698D1 (en) FLOW INJECTION ANALYSIS.
DE3789987D1 (en) A semiconductor memory device with a test mode and a standard mode operation.
DE68926227T2 (en) Field effect semiconductor arrangement with Schottky gate
DE3583718D1 (en) HOLE HOLE TOOL WITH SELECTABLE DIVERSION.
DE58905102D1 (en) ADJUSTABLE QUARTER POLE WITH CONSTANT INPUT AND OUTPUT RESISTANCE.
DE68922770D1 (en) Charge injection device with low noise output.
FR2507028A1 (en) ELECTRONIC CIRCUIT DEVICE, ESPECIALLY FOR USE IN AN ELECTRICALLY PROGRAMMABLE DEAD MEMORY
JPS57209503A (en) Sequence controller
BE819237A (en) JOSEPHSON'S JUNCTION MEMORY
FR1500487A (en) Improvements in timing mechanisms controlling the execution of an operations program
DE58909814D1 (en) Timing relay
BR8201020A (en) SPLIT FISHING DEVICE WELL AS A PULLEY AND DRAWING DEVICE EMPLOYED IN THE SAME
DE3577788D1 (en) Logical coincidence gate and logic sequential circuits using it.
FR1460735A (en) Ammonia distribution system on reversible and quarter-turn plows
SU588624A1 (en) Device for visual indication of pulses
SU1083202A1 (en) Device for determining extremum times
FR1489273A (en) Memory pulse program
SU1160238A1 (en) Thread checking device