JPS5694436A - Division error detecting system - Google Patents

Division error detecting system

Info

Publication number
JPS5694436A
JPS5694436A JP17336479A JP17336479A JPS5694436A JP S5694436 A JPS5694436 A JP S5694436A JP 17336479 A JP17336479 A JP 17336479A JP 17336479 A JP17336479 A JP 17336479A JP S5694436 A JPS5694436 A JP S5694436A
Authority
JP
Japan
Prior art keywords
register
output
circuit
subtractor
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17336479A
Other languages
Japanese (ja)
Other versions
JPS6046449B2 (en
Inventor
Takashi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54173364A priority Critical patent/JPS6046449B2/en
Publication of JPS5694436A publication Critical patent/JPS5694436A/en
Publication of JPS6046449B2 publication Critical patent/JPS6046449B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To output the error signal with a simple constitution, by adding a comparatively simple hardware to detect the error of the control system of the dividing device.
CONSTITUTION: In the repeated operation cycle, the dividend from devidend A register 1 is applied to control signal generating circuits 8 and 9, and is applied to adder and subtractor 10 for operation between the partial remainder and a proper multiple of the divisor. One of outputs of circuits 8 and 9 is selected according to the signal of adder and subtractor 10 by selecting circuit 11, and the output is stored in register 12. The multiple of the divisor determined by contents of register 12 and the divisor from D register 2 where the multiplier is stored are added or subtracted by adder and subtractor 10, and the partial remainder of the result is stored in register 14. The quotient is forecasted on a basis of the output of register 12 by forecasting circuit 13, and the quotient is forecasted on a basis of the output of register 14 by forecasting circuit 15, and outputs of forecasting circuits 13 and 15 are compared with each other by comparing circuit 16; and if they do not agree with each other, the error is output from comparing circuit 16.
COPYRIGHT: (C)1981,JPO&Japio
JP54173364A 1979-12-27 1979-12-27 Division error detection method Expired JPS6046449B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54173364A JPS6046449B2 (en) 1979-12-27 1979-12-27 Division error detection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54173364A JPS6046449B2 (en) 1979-12-27 1979-12-27 Division error detection method

Publications (2)

Publication Number Publication Date
JPS5694436A true JPS5694436A (en) 1981-07-30
JPS6046449B2 JPS6046449B2 (en) 1985-10-16

Family

ID=15959024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54173364A Expired JPS6046449B2 (en) 1979-12-27 1979-12-27 Division error detection method

Country Status (1)

Country Link
JP (1) JPS6046449B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198645A (en) * 1984-03-22 1985-10-08 Fujitsu Ltd Data processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198645A (en) * 1984-03-22 1985-10-08 Fujitsu Ltd Data processing system

Also Published As

Publication number Publication date
JPS6046449B2 (en) 1985-10-16

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