JPS5690352A - System diagnostic system - Google Patents

System diagnostic system

Info

Publication number
JPS5690352A
JPS5690352A JP16901079A JP16901079A JPS5690352A JP S5690352 A JPS5690352 A JP S5690352A JP 16901079 A JP16901079 A JP 16901079A JP 16901079 A JP16901079 A JP 16901079A JP S5690352 A JPS5690352 A JP S5690352A
Authority
JP
Japan
Prior art keywords
time
idle time
trigger
dead lock
timer tmr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16901079A
Other languages
Japanese (ja)
Inventor
Yuji Terauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16901079A priority Critical patent/JPS5690352A/en
Publication of JPS5690352A publication Critical patent/JPS5690352A/en
Pending legal-status Critical Current

Links

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To detect at an early stage the dead lock which occurs in the system, by detecting a stop factor of the system by use of an idle time of the system.
CONSTITUTION: The operating system OS sends a set signal to the time supervisory timer TMR at every idle time, and sends out a reset signal to the timer TMR whenever the effective interruption following said idle time is generated. When the timer TMR has received the set signal, it starts to count elapsing of a fixed time, and transmits the trigger to the diagnostic control means when the prescribed time has elapsed before receiving the reset signal. The control means DIAC analyzes the cause of the trigger according to said trigger, and starts the dead lock detection means DIAP by elapsing of the idle time. The detection means DIAP checks up the queue of each resource of the system OS, and detects the dead lock at an early stage.
COPYRIGHT: (C)1981,JPO&Japio
JP16901079A 1979-12-25 1979-12-25 System diagnostic system Pending JPS5690352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16901079A JPS5690352A (en) 1979-12-25 1979-12-25 System diagnostic system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16901079A JPS5690352A (en) 1979-12-25 1979-12-25 System diagnostic system

Publications (1)

Publication Number Publication Date
JPS5690352A true JPS5690352A (en) 1981-07-22

Family

ID=15878655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16901079A Pending JPS5690352A (en) 1979-12-25 1979-12-25 System diagnostic system

Country Status (1)

Country Link
JP (1) JPS5690352A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027956A (en) * 1983-07-26 1985-02-13 Fujitsu Ltd Self-diagnostic system
JPH04248200A (en) * 1991-01-09 1992-09-03 Nec Corp Fault monitor circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027956A (en) * 1983-07-26 1985-02-13 Fujitsu Ltd Self-diagnostic system
JPH04248200A (en) * 1991-01-09 1992-09-03 Nec Corp Fault monitor circuit

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