JPS5688540A - Interrupt control system - Google Patents

Interrupt control system

Info

Publication number
JPS5688540A
JPS5688540A JP16654179A JP16654179A JPS5688540A JP S5688540 A JPS5688540 A JP S5688540A JP 16654179 A JP16654179 A JP 16654179A JP 16654179 A JP16654179 A JP 16654179A JP S5688540 A JPS5688540 A JP S5688540A
Authority
JP
Japan
Prior art keywords
interrupt
processing
input
output
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16654179A
Other languages
Japanese (ja)
Inventor
Shinji Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16654179A priority Critical patent/JPS5688540A/en
Publication of JPS5688540A publication Critical patent/JPS5688540A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve the processing efficiency of a processing system, to which input-output devices are connected, by shortening its latency time by dividing the interrupt request of an input-output device into acceptance processing and interrupt analysis processing for performance.
CONSTITUTION: Interrupt requests R1, R2 and R3 from input-output devices are accepted at input-output interrupt level B, but a processing program running at this time is divided into two. Namely, only interrupt acceptance part 10 is run at input- output interrupt level B and interrupt information is made into a message. Further, interrupt processing parts 20 and 30 are run as process task 13' at task level E and the substantial processing of the interruption made into the message and return processing are performed at task levels. Thus, the time required for the interrupt processing can be shortened.
COPYRIGHT: (C)1981,JPO&Japio
JP16654179A 1979-12-21 1979-12-21 Interrupt control system Pending JPS5688540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16654179A JPS5688540A (en) 1979-12-21 1979-12-21 Interrupt control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16654179A JPS5688540A (en) 1979-12-21 1979-12-21 Interrupt control system

Publications (1)

Publication Number Publication Date
JPS5688540A true JPS5688540A (en) 1981-07-18

Family

ID=15833184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16654179A Pending JPS5688540A (en) 1979-12-21 1979-12-21 Interrupt control system

Country Status (1)

Country Link
JP (1) JPS5688540A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5197950A (en) * 1975-02-26 1976-08-28 Kanripuroguramuno seigyohoshiki
JPS51113435A (en) * 1975-03-28 1976-10-06 Hitachi Ltd Offering processor
JPS51135337A (en) * 1975-05-19 1976-11-24 Mitsubishi Electric Corp Data treatment device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5197950A (en) * 1975-02-26 1976-08-28 Kanripuroguramuno seigyohoshiki
JPS51113435A (en) * 1975-03-28 1976-10-06 Hitachi Ltd Offering processor
JPS51135337A (en) * 1975-05-19 1976-11-24 Mitsubishi Electric Corp Data treatment device

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