JPS5687225A - Skew correcting circuit - Google Patents

Skew correcting circuit

Info

Publication number
JPS5687225A
JPS5687225A JP16268279A JP16268279A JPS5687225A JP S5687225 A JPS5687225 A JP S5687225A JP 16268279 A JP16268279 A JP 16268279A JP 16268279 A JP16268279 A JP 16268279A JP S5687225 A JPS5687225 A JP S5687225A
Authority
JP
Japan
Prior art keywords
skew
data
contents
registers
detecting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16268279A
Other languages
Japanese (ja)
Inventor
Toshiki Okubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16268279A priority Critical patent/JPS5687225A/en
Publication of JPS5687225A publication Critical patent/JPS5687225A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce errors due to the skew by retrieving data in the direction of the skew even when the large skew exists in one data group.
CONSTITUTION: Data are set in data buffer 1, wind signal (g) of the 1st gate circuit 2 operates detecting circuit 3 for every track at its rise, and the 1st arrival dara enters detecting circuit 3. The contents of detecting circuit 3 are transferred to shift registers 4 and 5 after a certain time of the fall of wind signal (g), and those of the data buffer also enter registers 6 and 7. A CP signal is inputted to shift registers 4 and 5 to make shifts to right or left. Then, N CP terminals of shift registers 6 and 7 correspond to outputs, one to one, and the contents of data buffer 1 are transferred according to tracks. On the completion of the shifts, a parity ckeck is made and the contents of registers 6 and 7 are sent to skew buffer 11.
COPYRIGHT: (C)1981,JPO&Japio
JP16268279A 1979-12-17 1979-12-17 Skew correcting circuit Pending JPS5687225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16268279A JPS5687225A (en) 1979-12-17 1979-12-17 Skew correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16268279A JPS5687225A (en) 1979-12-17 1979-12-17 Skew correcting circuit

Publications (1)

Publication Number Publication Date
JPS5687225A true JPS5687225A (en) 1981-07-15

Family

ID=15759285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16268279A Pending JPS5687225A (en) 1979-12-17 1979-12-17 Skew correcting circuit

Country Status (1)

Country Link
JP (1) JPS5687225A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4746996A (en) * 1984-06-26 1988-05-24 Hitachi, Ltd. Skew error correction circuit for video signal reproducing apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4746996A (en) * 1984-06-26 1988-05-24 Hitachi, Ltd. Skew error correction circuit for video signal reproducing apparatus

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