JPS568435B2 - - Google Patents

Info

Publication number
JPS568435B2
JPS568435B2 JP9437072A JP9437072A JPS568435B2 JP S568435 B2 JPS568435 B2 JP S568435B2 JP 9437072 A JP9437072 A JP 9437072A JP 9437072 A JP9437072 A JP 9437072A JP S568435 B2 JPS568435 B2 JP S568435B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9437072A
Other languages
Japanese (ja)
Other versions
JPS4951833A (cg-RX-API-DMAC10.html
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9437072A priority Critical patent/JPS568435B2/ja
Priority to US00398340A priority patent/US3832699A/en
Priority to DE2347229A priority patent/DE2347229C3/de
Priority to GB4401973A priority patent/GB1451363A/en
Priority to IT29121/73A priority patent/IT993310B/it
Priority to FR7333634A priority patent/FR2200582B1/fr
Publication of JPS4951833A publication Critical patent/JPS4951833A/ja
Publication of JPS568435B2 publication Critical patent/JPS568435B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
JP9437072A 1972-09-19 1972-09-19 Expired JPS568435B2 (cg-RX-API-DMAC10.html)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP9437072A JPS568435B2 (cg-RX-API-DMAC10.html) 1972-09-19 1972-09-19
US00398340A US3832699A (en) 1972-09-19 1973-09-18 Memory control circuit
DE2347229A DE2347229C3 (de) 1972-09-19 1973-09-19 Schaltung zum Steuern des Adressier-, Lese-, Schreib- und Regeneriervorganges bei einem dynamischen Speicher
GB4401973A GB1451363A (en) 1972-09-19 1973-09-19 Memory circuits
IT29121/73A IT993310B (it) 1972-09-19 1973-09-19 Circuito per il rifornimento di cariche elettriche particolarmente per memorie di tipo dinamico
FR7333634A FR2200582B1 (cg-RX-API-DMAC10.html) 1972-09-19 1973-09-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9437072A JPS568435B2 (cg-RX-API-DMAC10.html) 1972-09-19 1972-09-19

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP54122869A Division JPS597159B2 (ja) 1979-09-25 1979-09-25 メモリ回路

Publications (2)

Publication Number Publication Date
JPS4951833A JPS4951833A (cg-RX-API-DMAC10.html) 1974-05-20
JPS568435B2 true JPS568435B2 (cg-RX-API-DMAC10.html) 1981-02-24

Family

ID=14108414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9437072A Expired JPS568435B2 (cg-RX-API-DMAC10.html) 1972-09-19 1972-09-19

Country Status (6)

Country Link
US (1) US3832699A (cg-RX-API-DMAC10.html)
JP (1) JPS568435B2 (cg-RX-API-DMAC10.html)
DE (1) DE2347229C3 (cg-RX-API-DMAC10.html)
FR (1) FR2200582B1 (cg-RX-API-DMAC10.html)
GB (1) GB1451363A (cg-RX-API-DMAC10.html)
IT (1) IT993310B (cg-RX-API-DMAC10.html)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3964030A (en) * 1973-12-10 1976-06-15 Bell Telephone Laboratories, Incorporated Semiconductor memory array
US4133611A (en) * 1977-07-08 1979-01-09 Xerox Corporation Two-page interweaved random access memory configuration
US4231110A (en) * 1979-01-29 1980-10-28 Fairchild Camera And Instrument Corp. Memory array with sequential row and column addressing
JPS55105893A (en) * 1979-01-31 1980-08-13 Sharp Corp Driving unit of dynamic memory
EP0067992A1 (en) * 1980-12-24 1983-01-05 Mostek Corporation Row driver circuit for semiconductor memory
US4338679A (en) * 1980-12-24 1982-07-06 Mostek Corporation Row driver circuit for semiconductor memory
US4404662A (en) * 1981-07-06 1983-09-13 International Business Machines Corporation Method and circuit for accessing an integrated semiconductor memory
JPS5957525A (ja) * 1982-09-28 1984-04-03 Fujitsu Ltd Ｃｍｉｓ回路装置
GB2360113B (en) * 2000-03-08 2004-11-10 Seiko Epson Corp Dynamic random access memory
US6711052B2 (en) * 2002-06-28 2004-03-23 Motorola, Inc. Memory having a precharge circuit and method therefor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3748651A (en) * 1972-02-16 1973-07-24 Cogar Corp Refresh control for add-on semiconductor memory
US3790961A (en) * 1972-06-09 1974-02-05 Advanced Memory Syst Inc Random access dynamic semiconductor memory system

Also Published As

Publication number Publication date
IT993310B (it) 1975-09-30
JPS4951833A (cg-RX-API-DMAC10.html) 1974-05-20
US3832699A (en) 1974-08-27
DE2347229B2 (de) 1978-03-23
DE2347229C3 (de) 1978-11-23
DE2347229A1 (de) 1974-05-02
FR2200582A1 (cg-RX-API-DMAC10.html) 1974-04-19
FR2200582B1 (cg-RX-API-DMAC10.html) 1977-10-07
GB1451363A (en) 1976-09-29

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