JPS55105893A - Driving unit of dynamic memory - Google Patents

Driving unit of dynamic memory

Info

Publication number
JPS55105893A
JPS55105893A JP1116579A JP1116579A JPS55105893A JP S55105893 A JPS55105893 A JP S55105893A JP 1116579 A JP1116579 A JP 1116579A JP 1116579 A JP1116579 A JP 1116579A JP S55105893 A JPS55105893 A JP S55105893A
Authority
JP
Japan
Prior art keywords
mode
power source
backup
control
under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1116579A
Other languages
Japanese (ja)
Other versions
JPS6259396B2 (en
Inventor
Shigeru Kitano
Hironori Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1116579A priority Critical patent/JPS55105893A/en
Priority to DE19803003524 priority patent/DE3003524C2/en
Publication of JPS55105893A publication Critical patent/JPS55105893A/en
Publication of JPS6259396B2 publication Critical patent/JPS6259396B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24Resetting means
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE: To secure the long-time backup of the memory even with the small-size battery by varying the control system for the refresh of the dynamic memory between the normal operation mode and the mode of the backup time by the battery.
CONSTITUTION: In the normal mode under which main body power source 22 is under the ON state, the operation is given to CPU21 and control means 24W26 with the power supply from power source 22 to give the write/read control or the refresh control of the data to dynamic RAM27. On the other hand, in the backup mode under which source 22 is under the OFF state, control means 25 and 26 have operation via battery power source 29 to give the refresh to RAM27. At the same time, detection means 23 detects the operation state of power source 22 and then delivers detection signal RES of H or L which indicates the normal mode or the backup mode. Signal RES is then turned into the reset or reset cancel signal of CPU21 and also contributes to switching of the control action in the both modes of means 25.
COPYRIGHT: (C)1980,JPO&Japio
JP1116579A 1979-01-31 1979-01-31 Driving unit of dynamic memory Granted JPS55105893A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1116579A JPS55105893A (en) 1979-01-31 1979-01-31 Driving unit of dynamic memory
DE19803003524 DE3003524C2 (en) 1979-01-31 1980-01-31 Refresh circuit for a dynamic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1116579A JPS55105893A (en) 1979-01-31 1979-01-31 Driving unit of dynamic memory

Publications (2)

Publication Number Publication Date
JPS55105893A true JPS55105893A (en) 1980-08-13
JPS6259396B2 JPS6259396B2 (en) 1987-12-10

Family

ID=11770423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1116579A Granted JPS55105893A (en) 1979-01-31 1979-01-31 Driving unit of dynamic memory

Country Status (2)

Country Link
JP (1) JPS55105893A (en)
DE (1) DE3003524C2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61271694A (en) * 1985-05-27 1986-12-01 Mitsubishi Electric Corp Memory device
JPH03130987A (en) * 1989-10-16 1991-06-04 Matsushita Graphic Commun Syst Inc Image communication equipment
US5640357A (en) * 1994-12-02 1997-06-17 Fujitsu Limited Storage device using dynamic RAM

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63285372A (en) * 1987-05-14 1988-11-22 Hitachi Metals Ltd Fluid controlling valve
JPH1115742A (en) * 1997-06-19 1999-01-22 Kofu Nippon Denki Kk Memory refresh control circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS568435B2 (en) * 1972-09-19 1981-02-24
DE2415029B2 (en) * 1974-03-28 1977-01-20 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt STORAGE SYSTEM SECURED AGAINST VOLTAGE FAILURE

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61271694A (en) * 1985-05-27 1986-12-01 Mitsubishi Electric Corp Memory device
JPH03130987A (en) * 1989-10-16 1991-06-04 Matsushita Graphic Commun Syst Inc Image communication equipment
US5640357A (en) * 1994-12-02 1997-06-17 Fujitsu Limited Storage device using dynamic RAM

Also Published As

Publication number Publication date
JPS6259396B2 (en) 1987-12-10
DE3003524A1 (en) 1980-08-07
DE3003524C2 (en) 1985-01-17

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