JPS5683157A - Synchronizer - Google Patents

Synchronizer

Info

Publication number
JPS5683157A
JPS5683157A JP15999379A JP15999379A JPS5683157A JP S5683157 A JPS5683157 A JP S5683157A JP 15999379 A JP15999379 A JP 15999379A JP 15999379 A JP15999379 A JP 15999379A JP S5683157 A JPS5683157 A JP S5683157A
Authority
JP
Japan
Prior art keywords
frame
synchronizing
partial frames
partial
synchronizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15999379A
Other languages
Japanese (ja)
Other versions
JPS6144426B2 (en
Inventor
Shigeo Nakatsuka
Takane Kakuno
Tachiki Ichihashi
Mitsuhiro Ishizaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15999379A priority Critical patent/JPS5683157A/en
Publication of JPS5683157A publication Critical patent/JPS5683157A/en
Publication of JPS6144426B2 publication Critical patent/JPS6144426B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates

Abstract

PURPOSE:To absorb jitter and to prevent malfunction, by performing delay correction to the frame in a loop transmission system and avoiding the missing of trailing of the preceding frame, when the synchronizing word enters the synchronizer and is again output. CONSTITUTION:A frame 4a taking the synchronizing word SYN as the head is fed to a synchronizer 1, it is converted into a parallel data at a serial/parallel conversion register SP, the synchronizing word SYN is detected at the synchronizing circuit FSYN, the partial frame number corresponding to partial frames D1-Dn is produced, and split instruction is given to a frame split circuit BUF. The partial frames D1-Dn and the frame number are written in the pushup memory FLFO, and the partial frames D1-Dn are stored in the frame memory FMEM as the unit word. Further, the partial frames D1-Dn are sequentially read out according to the sequence of write-in from the memory FMEM at the address counter CTOUT, they are converted into parallel data at a parallel serial conversion register PS, and they are transmitted to the transmission line by taking the synchronizing word SYM as the trailing.
JP15999379A 1979-12-10 1979-12-10 Synchronizer Granted JPS5683157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15999379A JPS5683157A (en) 1979-12-10 1979-12-10 Synchronizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15999379A JPS5683157A (en) 1979-12-10 1979-12-10 Synchronizer

Publications (2)

Publication Number Publication Date
JPS5683157A true JPS5683157A (en) 1981-07-07
JPS6144426B2 JPS6144426B2 (en) 1986-10-02

Family

ID=15705650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15999379A Granted JPS5683157A (en) 1979-12-10 1979-12-10 Synchronizer

Country Status (1)

Country Link
JP (1) JPS5683157A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58210736A (en) * 1982-06-02 1983-12-08 Yokogawa Hokushin Electric Corp Loop type data communication system
JPS6444652A (en) * 1987-08-13 1989-02-17 Nec Corp Loop data transmission system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03177228A (en) * 1989-12-07 1991-08-01 General Patsukaa Kk Stacked flexible tray separating device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50157008A (en) * 1974-06-07 1975-12-18
JPS535542A (en) * 1976-07-06 1978-01-19 Toshiba Corp Multiplication circular bus system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50157008A (en) * 1974-06-07 1975-12-18
JPS535542A (en) * 1976-07-06 1978-01-19 Toshiba Corp Multiplication circular bus system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58210736A (en) * 1982-06-02 1983-12-08 Yokogawa Hokushin Electric Corp Loop type data communication system
JPS6444652A (en) * 1987-08-13 1989-02-17 Nec Corp Loop data transmission system

Also Published As

Publication number Publication date
JPS6144426B2 (en) 1986-10-02

Similar Documents

Publication Publication Date Title
CA1212743A (en) Digital transmission systems
JPH0683172B2 (en) Frame alignment method
KR850004673A (en) Digital computer systems
JPS5683157A (en) Synchronizer
JP2643978B2 (en) Packet data generator
JPH069346B2 (en) Frequency conversion method for synchronous transmission
GB1311203A (en) Memory device
JP2758175B2 (en) Multiplexed frame conversion circuit
KR0121161Y1 (en) Switching system in common parallel bus
JP2970468B2 (en) Switch circuit with phase absorption function
SU1251075A1 (en) Device for unpacking instructions
KR950022982A (en) Splitter Design in Fully Digital High Definition Television
JP2957821B2 (en) Transmission memory control circuit
JPS63131735A (en) Multiplex frame aligner
JPS56109091A (en) Time slot replacing system
JPS54132135A (en) Memory control unit
SU1520480A1 (en) Program control device
JPH03255742A (en) Transmission repeater
JP2754574B2 (en) Asynchronous line synchronization circuit
JP3118518B2 (en) Digital communication equipment
JPS5850038A (en) Telemeter data processing device
JP3013011B2 (en) Buffer circuit
JPS62103729A (en) First-in first-out circuit
JPH05244130A (en) Clock converter
JPS5580965A (en) Memory control unit