JPS5679548A - Control system of loop type data transmission system - Google Patents
Control system of loop type data transmission systemInfo
- Publication number
- JPS5679548A JPS5679548A JP15564579A JP15564579A JPS5679548A JP S5679548 A JPS5679548 A JP S5679548A JP 15564579 A JP15564579 A JP 15564579A JP 15564579 A JP15564579 A JP 15564579A JP S5679548 A JPS5679548 A JP S5679548A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transmission
- fed
- reception
- transmission line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/437—Ring fault isolation or reconfiguration
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To enable automatic failure diagnosis of system and to decrease the restoration time at system down , by transmitting failures such as open transmission line and out of synchronism of station with one common transmission bus, in a loop system transmitting system. CONSTITUTION:A signal input to a reception circuit 18 via a transmission line 54 is respectively fed to a timing pickup circuit 19, demodulation circuit 26, and detection circuit 31 monitoring the presence of reception signal. The output of the timing pickup circuit 19 is fed to a PLL20 and fed to a control section 29 as reception clock and reception data. The transmission data from the control section 29 and the clock are fed to a modulation circuit 28 and fed to the next stage station via a transmission circuit 55 at the transmission circuit 30. If the reception signal transmitted from a transmission line 54 is absent, and if out of synchronism is caused, the detection circuits 31 and 27 detect it, logical sum is taken at a gate circuit 32 and the transmission restricting means 60 is operated with the output of the modulation circuit 28.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15564579A JPS5679548A (en) | 1979-12-03 | 1979-12-03 | Control system of loop type data transmission system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15564579A JPS5679548A (en) | 1979-12-03 | 1979-12-03 | Control system of loop type data transmission system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5679548A true JPS5679548A (en) | 1981-06-30 |
JPH0124383B2 JPH0124383B2 (en) | 1989-05-11 |
Family
ID=15610492
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15564579A Granted JPS5679548A (en) | 1979-12-03 | 1979-12-03 | Control system of loop type data transmission system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5679548A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5295104A (en) * | 1976-02-06 | 1977-08-10 | Hitachi Ltd | Data transmission device |
-
1979
- 1979-12-03 JP JP15564579A patent/JPS5679548A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5295104A (en) * | 1976-02-06 | 1977-08-10 | Hitachi Ltd | Data transmission device |
Also Published As
Publication number | Publication date |
---|---|
JPH0124383B2 (en) | 1989-05-11 |
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