JPS5678254A - Transmission system for digital code - Google Patents

Transmission system for digital code

Info

Publication number
JPS5678254A
JPS5678254A JP14298279A JP14298279A JPS5678254A JP S5678254 A JPS5678254 A JP S5678254A JP 14298279 A JP14298279 A JP 14298279A JP 14298279 A JP14298279 A JP 14298279A JP S5678254 A JPS5678254 A JP S5678254A
Authority
JP
Japan
Prior art keywords
signal
frame
intervals
display unit
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14298279A
Other languages
Japanese (ja)
Other versions
JPS5837737B2 (en
Inventor
Kazu Moriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP14298279A priority Critical patent/JPS5837737B2/en
Publication of JPS5678254A publication Critical patent/JPS5678254A/en
Publication of JPS5837737B2 publication Critical patent/JPS5837737B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To obtain a correct signal output even in interruption reception from the middle of a telegraphic message by sending a signal with start and stop signals, added at intervals of one frame, from a transmission side and by correcting frame display unit at a reception side. CONSTITUTION:At a reception side, error correction code adding device 2 adds a parity code to an input signal at intervals of one word and start and stop codes at intervals of one frame for interleaving 3, and synchronizing signal generation part 5 performs transmission by adding a synchronizing signal. At a reception side, the transmitted signal is demodulated 12 and the synchronizing signal is detected 18; after de-interleaving 15, error correction 16 is made and the obtained signal is outputted. Further, a frame-by-frame signal is differentiated and compared with a reference clock to detect 21 and 22 phase advance and delay, and the phase of clock CLK24 is adjusted to generate a set pulse and sample pulse. Furthermore, the demodulated signal is converted 13 into a parallel-bit signal, which is displayed on display unit 25 by way of buffer 14. Over a look at the lighting states of lamps of display unit 25, the phase of CLK24 is adjusted so as to perform frame synchronization.
JP14298279A 1979-11-05 1979-11-05 Digital code transmission method Expired JPS5837737B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14298279A JPS5837737B2 (en) 1979-11-05 1979-11-05 Digital code transmission method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14298279A JPS5837737B2 (en) 1979-11-05 1979-11-05 Digital code transmission method

Publications (2)

Publication Number Publication Date
JPS5678254A true JPS5678254A (en) 1981-06-27
JPS5837737B2 JPS5837737B2 (en) 1983-08-18

Family

ID=15328169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14298279A Expired JPS5837737B2 (en) 1979-11-05 1979-11-05 Digital code transmission method

Country Status (1)

Country Link
JP (1) JPS5837737B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003021453A2 (en) * 2001-08-29 2003-03-13 Analog Devices, Inc. Generic serial port architecture and system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003021453A2 (en) * 2001-08-29 2003-03-13 Analog Devices, Inc. Generic serial port architecture and system
WO2003021453A3 (en) * 2001-08-29 2004-03-18 Analog Devices Inc Generic serial port architecture and system
US7114093B2 (en) 2001-08-29 2006-09-26 Analog Devices, Inc. Generic architecture and system for a programmable serial port having a shift register and state machine therein

Also Published As

Publication number Publication date
JPS5837737B2 (en) 1983-08-18

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