JPS5674745A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5674745A
JPS5674745A JP15098879A JP15098879A JPS5674745A JP S5674745 A JPS5674745 A JP S5674745A JP 15098879 A JP15098879 A JP 15098879A JP 15098879 A JP15098879 A JP 15098879A JP S5674745 A JPS5674745 A JP S5674745A
Authority
JP
Japan
Prior art keywords
data
register
bit
memory
shifted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15098879A
Other languages
Japanese (ja)
Inventor
Kinichi Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15098879A priority Critical patent/JPS5674745A/en
Publication of JPS5674745A publication Critical patent/JPS5674745A/en
Pending legal-status Critical Current

Links

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To prevent a delay of the data processing by the regenerative work of a data, by regenerating a compressed data to its original data by means of hardware, in the data processing system for compressing an input data.
CONSTITUTION: When the head address of a compressed data is set into the memory address register 12 by the program, a flag data corresponding to the head address is input into the memory register 13. Its flag data is sent to the shift register 15 by decision of the channel control part 17, and it is shifted one bit by one bit. In case when the bit which has been shifted is "0", the data stored in the buffer register 19 at the last time is selected, and it is output as a regenerative data to the channel interface 20. Also, in case when the bit which has been shifted is "1", a data which has been read out to the memory data register 13 from the memory is output as a regenerative data.
COPYRIGHT: (C)1981,JPO&Japio
JP15098879A 1979-11-21 1979-11-21 Data processing system Pending JPS5674745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15098879A JPS5674745A (en) 1979-11-21 1979-11-21 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15098879A JPS5674745A (en) 1979-11-21 1979-11-21 Data processing system

Publications (1)

Publication Number Publication Date
JPS5674745A true JPS5674745A (en) 1981-06-20

Family

ID=15508822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15098879A Pending JPS5674745A (en) 1979-11-21 1979-11-21 Data processing system

Country Status (1)

Country Link
JP (1) JPS5674745A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60109356A (en) * 1983-11-18 1985-06-14 Brother Ind Ltd Data receiver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60109356A (en) * 1983-11-18 1985-06-14 Brother Ind Ltd Data receiver
JPH0135536B2 (en) * 1983-11-18 1989-07-26 Brother Ind Ltd

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