JPS566456A - Packaging method of semiconductor device - Google Patents

Packaging method of semiconductor device

Info

Publication number
JPS566456A
JPS566456A JP8233479A JP8233479A JPS566456A JP S566456 A JPS566456 A JP S566456A JP 8233479 A JP8233479 A JP 8233479A JP 8233479 A JP8233479 A JP 8233479A JP S566456 A JPS566456 A JP S566456A
Authority
JP
Japan
Prior art keywords
hole
semiconductor device
frame
resin
simplify
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8233479A
Other languages
Japanese (ja)
Other versions
JPS608626B2 (en
Inventor
Masayuki Kataoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8233479A priority Critical patent/JPS608626B2/en
Publication of JPS566456A publication Critical patent/JPS566456A/en
Publication of JPS608626B2 publication Critical patent/JPS608626B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PURPOSE:To simplify and facilitate a sealing work of a semiconductor device by forming a cover material formed with a hole for ventilating air of a thermoplastic resin package material when packaging a semiconductor device in a frame and heating to fuse and to block the hole of the cover material. CONSTITUTION:A frame 3 surrounding a bottom plate 2 carrying a semiconductor part 1 attached with a semiconductor device is mounted on the bottom plate 2, and silicone resin 4 or the like is filled in the frame to protect the semiconductor part. A thermoplastic resin cover 5' formed with a hole 7' for ventilating air is bonded to the frame 3 with resin 6, and a hot bar 9 such as the end of a soldering iron is urged toward the upper portion of the hole 7' so as to block the hole by fusing the resin around the hole. In this manner, the hole is simply and easily blocked so as to simplify the packaging work of the semiconductor device.
JP8233479A 1979-06-26 1979-06-26 Packaging method for semiconductor devices Expired JPS608626B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8233479A JPS608626B2 (en) 1979-06-26 1979-06-26 Packaging method for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8233479A JPS608626B2 (en) 1979-06-26 1979-06-26 Packaging method for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS566456A true JPS566456A (en) 1981-01-23
JPS608626B2 JPS608626B2 (en) 1985-03-04

Family

ID=13771655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8233479A Expired JPS608626B2 (en) 1979-06-26 1979-06-26 Packaging method for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS608626B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5038903A (en) * 1973-08-10 1975-04-10
JPS57188850A (en) * 1981-05-15 1982-11-19 Matsushita Electric Ind Co Ltd Sealing method for semiconductor element
JPS58140642U (en) * 1982-03-15 1983-09-21 日本電気株式会社 Hybrid IC case enclosure structure
JPH06504744A (en) * 1991-11-22 1994-06-02 メムテック・アメリカ・コーポレイション Stainless steel yarn and protective clothing
JP2014209570A (en) * 2013-03-29 2014-11-06 オムロン株式会社 Electronic apparatus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5038903A (en) * 1973-08-10 1975-04-10
JPS5735331B2 (en) * 1973-08-10 1982-07-28
JPS57188850A (en) * 1981-05-15 1982-11-19 Matsushita Electric Ind Co Ltd Sealing method for semiconductor element
JPS58140642U (en) * 1982-03-15 1983-09-21 日本電気株式会社 Hybrid IC case enclosure structure
JPS6225891Y2 (en) * 1982-03-15 1987-07-02
JPH06504744A (en) * 1991-11-22 1994-06-02 メムテック・アメリカ・コーポレイション Stainless steel yarn and protective clothing
JP2014209570A (en) * 2013-03-29 2014-11-06 オムロン株式会社 Electronic apparatus

Also Published As

Publication number Publication date
JPS608626B2 (en) 1985-03-04

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