JPS5660115A - Fail-safe type noncontact relay - Google Patents

Fail-safe type noncontact relay

Info

Publication number
JPS5660115A
JPS5660115A JP13514579A JP13514579A JPS5660115A JP S5660115 A JPS5660115 A JP S5660115A JP 13514579 A JP13514579 A JP 13514579A JP 13514579 A JP13514579 A JP 13514579A JP S5660115 A JPS5660115 A JP S5660115A
Authority
JP
Japan
Prior art keywords
output
input
fetqb
fetqa
saturated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13514579A
Other languages
Japanese (ja)
Other versions
JPS6230537B2 (en
Inventor
Takashi Enomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyosan Electric Manufacturing Co Ltd
Original Assignee
Kyosan Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyosan Electric Manufacturing Co Ltd filed Critical Kyosan Electric Manufacturing Co Ltd
Priority to JP13514579A priority Critical patent/JPS5660115A/en
Publication of JPS5660115A publication Critical patent/JPS5660115A/en
Publication of JPS6230537B2 publication Critical patent/JPS6230537B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To reduce electric power consumption and to fulfill miniaturization by putting two level detecting circuits into mutually complementary operation according to the saturated or unsaturated state of the amplifying circuit of FET by using a DC input voltage as a logical input. CONSTITUTION:When DC logical input A is 0, FETQB operates as an FET amplifier of a zero bias and output B' is generated. When no input arrives at FETQA, on the other hand, output B is 0. As logical input A changes into 1, an AC signal is amplified by FETQA and large AC output is generated by resistance RLA, so that output B may be 1. In this state, the DC voltage of the input of terminal A is applied to the gate of FETQB, which is saturated at a positive potential as compared with its source. Therefore, the saturation phenomenon of FETQB generates only an extremely small output across resistance RLB by the AC signal from terminal C and B' is 0.
JP13514579A 1979-10-22 1979-10-22 Fail-safe type noncontact relay Granted JPS5660115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13514579A JPS5660115A (en) 1979-10-22 1979-10-22 Fail-safe type noncontact relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13514579A JPS5660115A (en) 1979-10-22 1979-10-22 Fail-safe type noncontact relay

Publications (2)

Publication Number Publication Date
JPS5660115A true JPS5660115A (en) 1981-05-23
JPS6230537B2 JPS6230537B2 (en) 1987-07-02

Family

ID=15144853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13514579A Granted JPS5660115A (en) 1979-10-22 1979-10-22 Fail-safe type noncontact relay

Country Status (1)

Country Link
JP (1) JPS5660115A (en)

Also Published As

Publication number Publication date
JPS6230537B2 (en) 1987-07-02

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