JPS5658791A - Speed controlling device of dc motor - Google Patents
Speed controlling device of dc motorInfo
- Publication number
- JPS5658791A JPS5658791A JP13478279A JP13478279A JPS5658791A JP S5658791 A JPS5658791 A JP S5658791A JP 13478279 A JP13478279 A JP 13478279A JP 13478279 A JP13478279 A JP 13478279A JP S5658791 A JPS5658791 A JP S5658791A
- Authority
- JP
- Japan
- Prior art keywords
- rotation
- latch circuit
- frequency
- pulse
- entered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
- H02P23/22—Controlling the speed digitally using a reference oscillator, a speed proportional pulse rate feedback and a digital comparator
Abstract
PURPOSE:To eliminate the influence of temperature and the power source voltage fluctuation and to improve the stability of rotation frequency by a method wherein the detection information of frequency proportional to rotation frequency is processed through binary numeral and then, it is converted through a D/A converter. CONSTITUTION:A frequency generator G is connected to the DC motor M and detection signals of the frequency generator G are entered sequentially in one shot circuits O1-O4 to obtain six kinds of rotation pulses Q1-Q4. The rotation pulse Q4 and the reference pulse P1 from the pulse generation circuit POC are entered in the 1st counter C1 and between those phase differences, the 1st clock pulse P2 is counted and the output is held in a latch circuit L1. And further, rotation pulses Q2 and Q3 are entered in the 2nd counter C2 and the 2nd clock pulse P2 is counted between those phase differences and at this time, the initial value of a latch circuit L2 is made to be a value of the latch circuit L1. And the output of the latch circuit L2 is converted through the D/A converter to produce a speed error signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13478279A JPS5658791A (en) | 1979-10-18 | 1979-10-18 | Speed controlling device of dc motor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13478279A JPS5658791A (en) | 1979-10-18 | 1979-10-18 | Speed controlling device of dc motor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5658791A true JPS5658791A (en) | 1981-05-21 |
Family
ID=15136419
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13478279A Pending JPS5658791A (en) | 1979-10-18 | 1979-10-18 | Speed controlling device of dc motor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5658791A (en) |
-
1979
- 1979-10-18 JP JP13478279A patent/JPS5658791A/en active Pending
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