JPS5655042A - Positioning of mask and wafer - Google Patents

Positioning of mask and wafer

Info

Publication number
JPS5655042A
JPS5655042A JP12998679A JP12998679A JPS5655042A JP S5655042 A JPS5655042 A JP S5655042A JP 12998679 A JP12998679 A JP 12998679A JP 12998679 A JP12998679 A JP 12998679A JP S5655042 A JPS5655042 A JP S5655042A
Authority
JP
Japan
Prior art keywords
mask
wafer
stage
positioning
size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12998679A
Other languages
Japanese (ja)
Other versions
JPS6053458B2 (en
Inventor
Toshiyuki Horiuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54129986A priority Critical patent/JPS6053458B2/en
Publication of JPS5655042A publication Critical patent/JPS5655042A/en
Publication of JPS6053458B2 publication Critical patent/JPS6053458B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Control Of Position Or Direction (AREA)

Abstract

PURPOSE:To accurately position on the entire surface of a large-diameter wafer by imparting an elongation or a contraction in opposite direction to the relative elongation or contraction occurred due to certain cause between the mask and the wafer to the mask and the wafer, thereby eliminating the size difference between the mask and the wafer. CONSTITUTION:When a mask 1 having a thickness t is slackened in an infinitesimal amount delta indicated by a broken line, there occurs a size variation of 4deltat/l between the surface 2 of the mask and the surface 3 of the mask when slackened as the length of the surface of the mask is represented by l. The mask 4 is adsorbed to a mask stage 5, a wafer 6 is adsorbed to a wafer stage 7, and positioning is conducted in this state. Subsequently, the stage 8 is raised, and the wafer 6 is urged onto the mask 4 by a spring 9. When the space between the mask 4 and the wafer 6 is evacuated to a vacuum and the adsorption to the wafer stage is eliminated so that both are brought into contact with each other, the size of the wafer 6 is varied. Then, the stage 8 is elevationally slacked variably, and positioning is conducted accurately on the entire surface.
JP54129986A 1979-10-11 1979-10-11 How to align masks and wafers Expired JPS6053458B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54129986A JPS6053458B2 (en) 1979-10-11 1979-10-11 How to align masks and wafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54129986A JPS6053458B2 (en) 1979-10-11 1979-10-11 How to align masks and wafers

Publications (2)

Publication Number Publication Date
JPS5655042A true JPS5655042A (en) 1981-05-15
JPS6053458B2 JPS6053458B2 (en) 1985-11-26

Family

ID=15023324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54129986A Expired JPS6053458B2 (en) 1979-10-11 1979-10-11 How to align masks and wafers

Country Status (1)

Country Link
JP (1) JPS6053458B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0473766A (en) * 1990-07-16 1992-03-09 Toshiba Corp Proximity exposure device
CN103572342A (en) * 2012-07-23 2014-02-12 崇鼎科技有限公司 Shielding method for local surface treatment
US8871106B2 (en) * 2012-07-13 2014-10-28 Apone Technology Ltd. Masking method for locally treating surface

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0231656U (en) * 1988-08-22 1990-02-28
JPH02104958U (en) * 1989-01-31 1990-08-21
JPH05177530A (en) * 1991-12-26 1993-07-20 Tomio Ino Granular substance polishing device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0473766A (en) * 1990-07-16 1992-03-09 Toshiba Corp Proximity exposure device
US8871106B2 (en) * 2012-07-13 2014-10-28 Apone Technology Ltd. Masking method for locally treating surface
CN103572342A (en) * 2012-07-23 2014-02-12 崇鼎科技有限公司 Shielding method for local surface treatment

Also Published As

Publication number Publication date
JPS6053458B2 (en) 1985-11-26

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