JPS5654700A - Test method of memory element and test pattern generator for the said test - Google Patents

Test method of memory element and test pattern generator for the said test

Info

Publication number
JPS5654700A
JPS5654700A JP13121879A JP13121879A JPS5654700A JP S5654700 A JPS5654700 A JP S5654700A JP 13121879 A JP13121879 A JP 13121879A JP 13121879 A JP13121879 A JP 13121879A JP S5654700 A JPS5654700 A JP S5654700A
Authority
JP
Japan
Prior art keywords
address
sets
test
patterns
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13121879A
Other languages
Japanese (ja)
Inventor
Kazumitsu Matsuzawa
Tsutomu Ishikawa
Noboru Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13121879A priority Critical patent/JPS5654700A/en
Publication of JPS5654700A publication Critical patent/JPS5654700A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To ensure a perfect detection for the address fault of less than the prescribed bits as well as the defect of the memory cell array, by dividing the whole memory region of the memory element into the sets of the address patterns having the fixed minimum distance and then giving an address to these sets with different data.
CONSTITUTION: The sets S1WS8 are constituted so that the address patterns within the sets may have the Hamming distance (d) of 3 or more to each other. Thus both the defect of the memory cell array and the address fault of d-1 bits or less are detected via each address pattern. For the test pattern generator, the contents of the counter 2 is 0 for the first 2K cycles, and the output of the logic circuit 5 becomes equal to the output of the logic arithmetic means 4. For the address pattern 6, the coding is given to the output of the counter 1 by the grown matrix and in the form of the information bit, and the address patterns in the set S1 are generated successively. In the next 2K cycles, the bits are added by the address pattern method 2, and the address patterns in the set S2 are generated successively. Then the address patterns in the sets S3WS8 are generated in the same way.
COPYRIGHT: (C)1981,JPO&Japio
JP13121879A 1979-10-11 1979-10-11 Test method of memory element and test pattern generator for the said test Pending JPS5654700A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13121879A JPS5654700A (en) 1979-10-11 1979-10-11 Test method of memory element and test pattern generator for the said test

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13121879A JPS5654700A (en) 1979-10-11 1979-10-11 Test method of memory element and test pattern generator for the said test

Publications (1)

Publication Number Publication Date
JPS5654700A true JPS5654700A (en) 1981-05-14

Family

ID=15052789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13121879A Pending JPS5654700A (en) 1979-10-11 1979-10-11 Test method of memory element and test pattern generator for the said test

Country Status (1)

Country Link
JP (1) JPS5654700A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2412453A (en) * 2004-03-27 2005-09-28 David Hostettler Wain 6/3 Hamming Error Correction
JP2015072727A (en) * 2013-10-03 2015-04-16 富士通セミコンダクター株式会社 Ferroelectric memory device, and memory writing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2412453A (en) * 2004-03-27 2005-09-28 David Hostettler Wain 6/3 Hamming Error Correction
JP2015072727A (en) * 2013-10-03 2015-04-16 富士通セミコンダクター株式会社 Ferroelectric memory device, and memory writing method

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