JPS5647189A - Pedestal clamp keying pulse generating circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit that suits to be IC-implemented and can secure stable operation against noises, by providing a counting circuit that counts clock pulses of a local subcarrier signal for a fixed time from the trailing edge of a horizontal synchronizing signal. CONSTITUTION:To input terminal 41 of keying pulse generating circuit 30, a local chrominance subcarrier signal is supplied as clock pulses and to input terminal 42, a horizontal synchronizing signal is further supplied as reset pulses. Then, counting circuit 46 counts clock pulses for a fixed time from the trailing edge of the horizontal synchronizing signal and when its count value reaches a fixed value, flip-flop FF5 is reset. Pulses of the fixed count value of counting circuit 52 reset with the output of AND between the output of FF5 and a fly-back pulse supplied from input terminal 33 of no-signal deciding circuit 32 are inputted to latch circuit 55 together with the output of logic circuit 50. According to the state of this latch circuit 55, output pulses of logic circuit 50 or fly-back pulses are sent to keying pulse output terminal 62.