JPS5644866A - Measurement of breakdown strength of latch circuit - Google Patents

Measurement of breakdown strength of latch circuit

Info

Publication number
JPS5644866A
JPS5644866A JP12066379A JP12066379A JPS5644866A JP S5644866 A JPS5644866 A JP S5644866A JP 12066379 A JP12066379 A JP 12066379A JP 12066379 A JP12066379 A JP 12066379A JP S5644866 A JPS5644866 A JP S5644866A
Authority
JP
Japan
Prior art keywords
voltage
pulse
integrated circuit
generator
mos integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12066379A
Other languages
Japanese (ja)
Inventor
Toshiharu Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12066379A priority Critical patent/JPS5644866A/en
Publication of JPS5644866A publication Critical patent/JPS5644866A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE: To distinguish the degradability by adding pulse to a counter and then to a stepped wave generator, and applying this stepped wave to a C-MOS integrated circuit and stopping the pulse when an abnormal electric current has exceeded beyond a prearranged value.
CONSTITUTION: The pulse is added to the counter 2 from a pulse generator 1 and then is input to the step pulse generator 9. The step pulse from the generator 9 is applied to the C-MOS integrated circuit 12 and its abnormal electric current is converted to voltage by means of resistor 13. This voltage is compared with reference voltage 14 with the assistance of a comparator 15. When voltage of the resistor 13 has exceeded the reference voltage 14, it is held on a voltage-holding circuit 16 and power supply voltage for the C-MOS integrated circuit is reduced to nothing by means of a switching part 17. At the same time, the pulse generator 1 is stopped. The quality of the C-MOS integrated circuit is determined, depending on the details of the counter 2.
COPYRIGHT: (C)1981,JPO&Japio
JP12066379A 1979-09-21 1979-09-21 Measurement of breakdown strength of latch circuit Pending JPS5644866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12066379A JPS5644866A (en) 1979-09-21 1979-09-21 Measurement of breakdown strength of latch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12066379A JPS5644866A (en) 1979-09-21 1979-09-21 Measurement of breakdown strength of latch circuit

Publications (1)

Publication Number Publication Date
JPS5644866A true JPS5644866A (en) 1981-04-24

Family

ID=14791812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12066379A Pending JPS5644866A (en) 1979-09-21 1979-09-21 Measurement of breakdown strength of latch circuit

Country Status (1)

Country Link
JP (1) JPS5644866A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57163876A (en) * 1981-03-31 1982-10-08 Mitsubishi Electric Corp Measuring method for latch-up dielectric strength of complementary mos integrated-circuit device
JPS61256266A (en) * 1985-05-09 1986-11-13 Rohm Co Ltd Measurement for latch up phenomenon of cmos element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57163876A (en) * 1981-03-31 1982-10-08 Mitsubishi Electric Corp Measuring method for latch-up dielectric strength of complementary mos integrated-circuit device
JPH0147751B2 (en) * 1981-03-31 1989-10-16 Mitsubishi Electric Corp
JPS61256266A (en) * 1985-05-09 1986-11-13 Rohm Co Ltd Measurement for latch up phenomenon of cmos element

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