JPS5643831A - Lamination type cmos semiconductor device - Google Patents

Lamination type cmos semiconductor device

Info

Publication number
JPS5643831A
JPS5643831A JP11979679A JP11979679A JPS5643831A JP S5643831 A JPS5643831 A JP S5643831A JP 11979679 A JP11979679 A JP 11979679A JP 11979679 A JP11979679 A JP 11979679A JP S5643831 A JPS5643831 A JP S5643831A
Authority
JP
Japan
Prior art keywords
semiconductor device
lamination type
type cmos
circuit
cmos semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11979679A
Other languages
Japanese (ja)
Inventor
Nobuo Inami
Kojiro Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP11979679A priority Critical patent/JPS5643831A/en
Publication of JPS5643831A publication Critical patent/JPS5643831A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To operate a semiconductor device with small electric power by connecting some of inverters in series to the electric power source of the semiconductor device. CONSTITUTION:Not only by controlling the threshold value of the transistor low but also by selecting constants of oscillating circuit 2, buffer circuit 3 and frequency- dividing circuit 4, I0=IB+ID is realized. Further, an interchange of signals is carried out between oscillating circuit 2 and buffer circuit 3. This can be realized by setting the threshold level of each transistor a quarter the power voltage in case of two-layer structure.
JP11979679A 1979-09-18 1979-09-18 Lamination type cmos semiconductor device Pending JPS5643831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11979679A JPS5643831A (en) 1979-09-18 1979-09-18 Lamination type cmos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11979679A JPS5643831A (en) 1979-09-18 1979-09-18 Lamination type cmos semiconductor device

Publications (1)

Publication Number Publication Date
JPS5643831A true JPS5643831A (en) 1981-04-22

Family

ID=14770429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11979679A Pending JPS5643831A (en) 1979-09-18 1979-09-18 Lamination type cmos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5643831A (en)

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