JPS5642421A - Waveform equalizer - Google Patents

Waveform equalizer

Info

Publication number
JPS5642421A
JPS5642421A JP11788179A JP11788179A JPS5642421A JP S5642421 A JPS5642421 A JP S5642421A JP 11788179 A JP11788179 A JP 11788179A JP 11788179 A JP11788179 A JP 11788179A JP S5642421 A JPS5642421 A JP S5642421A
Authority
JP
Japan
Prior art keywords
frequency
low
filter
frequency component
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11788179A
Other languages
Japanese (ja)
Inventor
Takehiro Murase
Kozo Morita
Masaharu Araki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11788179A priority Critical patent/JPS5642421A/en
Publication of JPS5642421A publication Critical patent/JPS5642421A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset

Abstract

PURPOSE:To attain high precision while simplifying the constitution of a unit by separately treating the low-frequency component and high-frequency component of an input signal, by correcting the high-frequency component by a transversal filter and then by correcting the low-frequency component by another correcting circuit. CONSTITUTION:An input signal from signal input terminal 1 is passed through low- frequency stopping filter 2 to remove a frequency component of its cut-off frequency or lower and its output signal is applied to delay circuit 3 having a tapped delay line; and signals lead out of the taps are applied to variable gain circuits 4 to give weight of proper polarity and their output signals are supplied to adder 5. Then, the DC and low-frequency components are previously removed from the input signal and the output signal of adder 5 is waveform-shaped by regenerator 7 and the DC and low-frequency components removed by filter 2 are extracted by high-frequency stopping filter 8, whose output is applied to adder 5 to compensate inter- code interference caused at filter 2 through waveform transmission.
JP11788179A 1979-09-17 1979-09-17 Waveform equalizer Pending JPS5642421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11788179A JPS5642421A (en) 1979-09-17 1979-09-17 Waveform equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11788179A JPS5642421A (en) 1979-09-17 1979-09-17 Waveform equalizer

Publications (1)

Publication Number Publication Date
JPS5642421A true JPS5642421A (en) 1981-04-20

Family

ID=14722542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11788179A Pending JPS5642421A (en) 1979-09-17 1979-09-17 Waveform equalizer

Country Status (1)

Country Link
JP (1) JPS5642421A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066441U (en) * 1983-10-07 1985-05-11 セイコー株式会社 Eyeglass lens aligner
JPH02141839U (en) * 1989-04-28 1990-11-29

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51115754A (en) * 1975-04-03 1976-10-12 Nec Corp Accommodation type automatic equalizer
JPS5314534A (en) * 1976-07-26 1978-02-09 Nippon Telegr & Teleph Corp <Ntt> Addition/subtraction circuit unit with variable weight

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51115754A (en) * 1975-04-03 1976-10-12 Nec Corp Accommodation type automatic equalizer
JPS5314534A (en) * 1976-07-26 1978-02-09 Nippon Telegr & Teleph Corp <Ntt> Addition/subtraction circuit unit with variable weight

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066441U (en) * 1983-10-07 1985-05-11 セイコー株式会社 Eyeglass lens aligner
JPH02141839U (en) * 1989-04-28 1990-11-29
JP2518284Y2 (en) * 1989-04-28 1996-11-27 グランド精工株式会社 Axis processing for unprocessed eyeglass lenses

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