JPS5641017B2 - - Google Patents

Info

Publication number
JPS5641017B2
JPS5641017B2 JP753794A JP379475A JPS5641017B2 JP S5641017 B2 JPS5641017 B2 JP S5641017B2 JP 753794 A JP753794 A JP 753794A JP 379475 A JP379475 A JP 379475A JP S5641017 B2 JPS5641017 B2 JP S5641017B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP753794A
Other languages
Japanese (ja)
Other versions
JPS5178679A (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP753794A priority Critical patent/JPS5641017B2/ja
Publication of JPS5178679A publication Critical patent/JPS5178679A/ja
Publication of JPS5641017B2 publication Critical patent/JPS5641017B2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
JP753794A 1974-12-28 1974-12-28 Expired JPS5641017B2 (en:Method)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP753794A JPS5641017B2 (en:Method) 1974-12-28 1974-12-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP753794A JPS5641017B2 (en:Method) 1974-12-28 1974-12-28

Publications (2)

Publication Number Publication Date
JPS5178679A JPS5178679A (en:Method) 1976-07-08
JPS5641017B2 true JPS5641017B2 (en:Method) 1981-09-25

Family

ID=11567086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP753794A Expired JPS5641017B2 (en:Method) 1974-12-28 1974-12-28

Country Status (1)

Country Link
JP (1) JPS5641017B2 (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043556A (ja) * 1983-08-17 1985-03-08 株式会社クボタ 降り棟の葺き上げ方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5658670A (en) * 1979-10-19 1981-05-21 Nippon Telegr & Teleph Corp <Ntt> Logical waveform generating circuit
JPS57111470A (en) * 1980-12-29 1982-07-10 Advantest Corp Logical-waveform generation circuit
JPS57174958A (en) * 1981-04-21 1982-10-27 Nec Corp Pseudo error pulse inserting circuit
GB2340277B (en) * 1995-02-24 2000-05-03 Advantest Corp Bit error measurement system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58163B2 (ja) * 1972-05-09 1983-01-05 住友電気工業株式会社 チヨウコウソクテツドウヨウチヨウデンドウマグネツト
FR2211169A5 (en:Method) * 1972-12-15 1974-07-12 Sle Citerel Lannion Elec

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043556A (ja) * 1983-08-17 1985-03-08 株式会社クボタ 降り棟の葺き上げ方法

Also Published As

Publication number Publication date
JPS5178679A (en:Method) 1976-07-08

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