JPS563490A - Magnetic bubble memory reading circuit - Google Patents

Magnetic bubble memory reading circuit

Info

Publication number
JPS563490A
JPS563490A JP7630279A JP7630279A JPS563490A JP S563490 A JPS563490 A JP S563490A JP 7630279 A JP7630279 A JP 7630279A JP 7630279 A JP7630279 A JP 7630279A JP S563490 A JPS563490 A JP S563490A
Authority
JP
Japan
Prior art keywords
output
magnetic bubble
bubble memory
logic output
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7630279A
Other languages
Japanese (ja)
Inventor
Kaneichi Otsuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7630279A priority Critical patent/JPS563490A/en
Publication of JPS563490A publication Critical patent/JPS563490A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enhance the S/N of the detection signal and then ensure the assured reading, by holding logic output 1 of the magnetic bubble memory until the end of the next strobe timing and then switching the discrimination reference level.
CONSTITUTION: Outputs C of bubble detectors 1a and 1b plus dummy detectors 2a and 2b are supplied to differential amplifier 5. Thus the in-phase induced noise is negated to be supplied to level discriminator 6a. Discriminator 6a transmits the logic output corresponding to 1 and 0 each of the output of the magnetic bubble memory and in synchronization with strobe timing STB. When the logic output is 1, FF7 is set and then reset in the clock section with no logic output 1 existing and after STB of the section. And the discrimination reference level is switched by output Q of FF7. As a result, the S/N is increased for the output waveform level of amplifier 5 to ensure the discrimination.
COPYRIGHT: (C)1981,JPO&Japio
JP7630279A 1979-06-19 1979-06-19 Magnetic bubble memory reading circuit Pending JPS563490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7630279A JPS563490A (en) 1979-06-19 1979-06-19 Magnetic bubble memory reading circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7630279A JPS563490A (en) 1979-06-19 1979-06-19 Magnetic bubble memory reading circuit

Publications (1)

Publication Number Publication Date
JPS563490A true JPS563490A (en) 1981-01-14

Family

ID=13601567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7630279A Pending JPS563490A (en) 1979-06-19 1979-06-19 Magnetic bubble memory reading circuit

Country Status (1)

Country Link
JP (1) JPS563490A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212681A (en) * 1981-06-24 1982-12-27 Hitachi Ltd Magnetic bubble memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212681A (en) * 1981-06-24 1982-12-27 Hitachi Ltd Magnetic bubble memory device
JPS613021B2 (en) * 1981-06-24 1986-01-29 Hitachi Ltd

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