JPS5460814A - Timing circuit of dipulse system - Google Patents

Timing circuit of dipulse system

Info

Publication number
JPS5460814A
JPS5460814A JP12795077A JP12795077A JPS5460814A JP S5460814 A JPS5460814 A JP S5460814A JP 12795077 A JP12795077 A JP 12795077A JP 12795077 A JP12795077 A JP 12795077A JP S5460814 A JPS5460814 A JP S5460814A
Authority
JP
Japan
Prior art keywords
pulse
divider
circuit
synchronization
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12795077A
Other languages
Japanese (ja)
Inventor
Kazuhiro Hiraide
Yoji Fukinuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP12795077A priority Critical patent/JPS5460814A/en
Publication of JPS5460814A publication Critical patent/JPS5460814A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To obtain the synchronization of the reproducing clock pulse by resetting the divider with the frame synchronous pulse, and then to secure application of the synchronization to the magnetic recording and others. CONSTITUTION:The signal modulated through the dipulse system is equalization- amplified to the binary code and then supplied through terminal 2. The pulse changing point is detected by code level changing point detector circuit 3 and applied to timing extraction circuit 11 to extract 2f0 and then to be applied to 1/2 divider 7 in the form of the clock pulse. On the other hand, the output of circuit 3 is applied to retriggerable monostable-multivibrator 9 to obtain the trigger output just before the frame synchronous pulse. The fall point of the trigger output is detected through circuit 10 to obtain the narrow trigger pulse to reset divider 7. Thus, the synchronous state can be secured in divider 7 through resetting via the frame synchronous pulse even though the clock is in the non-synchronous state at first, obtaining the timing at terminal 8.
JP12795077A 1977-10-25 1977-10-25 Timing circuit of dipulse system Pending JPS5460814A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12795077A JPS5460814A (en) 1977-10-25 1977-10-25 Timing circuit of dipulse system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12795077A JPS5460814A (en) 1977-10-25 1977-10-25 Timing circuit of dipulse system

Publications (1)

Publication Number Publication Date
JPS5460814A true JPS5460814A (en) 1979-05-16

Family

ID=14972640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12795077A Pending JPS5460814A (en) 1977-10-25 1977-10-25 Timing circuit of dipulse system

Country Status (1)

Country Link
JP (1) JPS5460814A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6039947A (en) * 1983-08-15 1985-03-02 Seiko Epson Corp Timing signal extracting circuit
JPS6039946A (en) * 1983-08-15 1985-03-02 Seiko Epson Corp Timing signal extracting circuit
EP0141916A2 (en) * 1983-08-30 1985-05-22 TELEFUNKEN Fernseh und Rundfunk GmbH Method for inserting a synchronisation pattern
JPH02264533A (en) * 1989-04-04 1990-10-29 Nec Corp Data transmission system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938443A (en) * 1972-08-19 1974-04-10
JPS501740A (en) * 1973-05-02 1975-01-09

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938443A (en) * 1972-08-19 1974-04-10
JPS501740A (en) * 1973-05-02 1975-01-09

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6039947A (en) * 1983-08-15 1985-03-02 Seiko Epson Corp Timing signal extracting circuit
JPS6039946A (en) * 1983-08-15 1985-03-02 Seiko Epson Corp Timing signal extracting circuit
EP0141916A2 (en) * 1983-08-30 1985-05-22 TELEFUNKEN Fernseh und Rundfunk GmbH Method for inserting a synchronisation pattern
JPH02264533A (en) * 1989-04-04 1990-10-29 Nec Corp Data transmission system

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