JPS5629727A - Reset signal generating circuit - Google Patents

Reset signal generating circuit

Info

Publication number
JPS5629727A
JPS5629727A JP10633879A JP10633879A JPS5629727A JP S5629727 A JPS5629727 A JP S5629727A JP 10633879 A JP10633879 A JP 10633879A JP 10633879 A JP10633879 A JP 10633879A JP S5629727 A JPS5629727 A JP S5629727A
Authority
JP
Japan
Prior art keywords
circuit
reset signal
terminal
transistors
power source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10633879A
Other languages
Japanese (ja)
Other versions
JPS5826049B2 (en
Inventor
Tsuneo Okubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP54106338A priority Critical patent/JPS5826049B2/en
Publication of JPS5629727A publication Critical patent/JPS5629727A/en
Publication of JPS5826049B2 publication Critical patent/JPS5826049B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To ensure a simple and assured generation of the reset signal during the ON and OFF of the power source and thus prevent the faulty operation, by providing three units of transistors and then performing the detection of the reset signal while the power source is on as well as the detection of the short break while the power source is off each through the combinations of the three transistors.
CONSTITUTION: Three transistors TR6, 9 and 10 are provided. The emitter of each transistor is connected to the output terminal B of the 2nd voltage 15V in the power supply circuit 1 via the resistance 11. And the collectors of the TR6 and 9 are connected to the reset terminal D of the integrated circuit 25 via the serial resistor 23, the time constant circuit 22 and then the TR20 each. The capacitor 3 is charged a little after the circuit 1 is switched on, and this charging voltage becomes higher than the base voltage of the TR10. At the same time, the TR6 is turned off, and the reset signal of the terminal D does not exist any more. On the other hand, the 1st power supply voltage 5V has a quick rise when the circuit 1 is switched off. And the TR9 is turned on with the TR20's collector biased negative each. Thus the terminal D is biased negative to prevent the faulty operation of the circuit 25.
COPYRIGHT: (C)1981,JPO&Japio
JP54106338A 1979-08-20 1979-08-20 Reset signal generation circuit Expired JPS5826049B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54106338A JPS5826049B2 (en) 1979-08-20 1979-08-20 Reset signal generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54106338A JPS5826049B2 (en) 1979-08-20 1979-08-20 Reset signal generation circuit

Publications (2)

Publication Number Publication Date
JPS5629727A true JPS5629727A (en) 1981-03-25
JPS5826049B2 JPS5826049B2 (en) 1983-05-31

Family

ID=14431059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54106338A Expired JPS5826049B2 (en) 1979-08-20 1979-08-20 Reset signal generation circuit

Country Status (1)

Country Link
JP (1) JPS5826049B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6426748U (en) * 1987-08-07 1989-02-15

Also Published As

Publication number Publication date
JPS5826049B2 (en) 1983-05-31

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