JPS562762A - Start-stop synchronous communication system - Google Patents

Start-stop synchronous communication system

Info

Publication number
JPS562762A
JPS562762A JP7755979A JP7755979A JPS562762A JP S562762 A JPS562762 A JP S562762A JP 7755979 A JP7755979 A JP 7755979A JP 7755979 A JP7755979 A JP 7755979A JP S562762 A JPS562762 A JP S562762A
Authority
JP
Japan
Prior art keywords
circuit
transmission
frequency
clocks
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7755979A
Other languages
Japanese (ja)
Inventor
Masamichi Hashimoto
Tokuhiro Aritaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7755979A priority Critical patent/JPS562762A/en
Publication of JPS562762A publication Critical patent/JPS562762A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00Arrangements affording multiple use of the transmission path
    • H04L5/14Two-way operation using the same type of signal, i.e. duplex
    • H04L5/1438Negotiation of transmission parameters prior to communication
    • H04L5/1446Negotiation of transmission parameters prior to communication of transmission speed

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To equalize the transmission speed between transmission and receiving, by using clocks of one frequency from the transmission side and by switching clocks successively from the maximum frequency to the minimum frequency for every occurrence of synchronization error and using them as receiving clocks. CONSTITUTION:Start-stop synchronous-system transmission circuit 10 is provided with parallel-series converter 18 which converts parallel transmission data D sent through line 16 to a series data, start bit adding circuit 20, parity check bit adding circuit 22, and stop bit adding circuit 24, and the clock of one frequency out of many kinds of frequency set previously is transmitted from the transmission side to data transmission line 14. Character synchronization errors are detected in stop bit detecting circuit 30 of receiving circuit 12, and clocks CK1-CKn set previously in clock selecting circuit 38 are switched successively for every occurrence of a character synchronization error by selection indicating circuit 40 to select one clock, and this clock is applied to series-parallel converter 32 and is output to line DR after equalizing the transmission speed to transmission circuit 10.
JP7755979A 1979-06-21 1979-06-21 Start-stop synchronous communication system Pending JPS562762A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7755979A JPS562762A (en) 1979-06-21 1979-06-21 Start-stop synchronous communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7755979A JPS562762A (en) 1979-06-21 1979-06-21 Start-stop synchronous communication system

Publications (1)

Publication Number Publication Date
JPS562762A true JPS562762A (en) 1981-01-13

Family

ID=13637366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7755979A Pending JPS562762A (en) 1979-06-21 1979-06-21 Start-stop synchronous communication system

Country Status (1)

Country Link
JP (1) JPS562762A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5941938A (en) * 1982-09-01 1984-03-08 Hitachi Ltd Automatic setting system of transmission speed
WO2020145001A1 (en) * 2019-01-11 2020-07-16 株式会社日立産機システム Crane and hoist

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5941938A (en) * 1982-09-01 1984-03-08 Hitachi Ltd Automatic setting system of transmission speed
WO2020145001A1 (en) * 2019-01-11 2020-07-16 株式会社日立産機システム Crane and hoist

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