JPS562662A - Laminated electric circuit - Google Patents

Laminated electric circuit

Info

Publication number
JPS562662A
JPS562662A JP7820479A JP7820479A JPS562662A JP S562662 A JPS562662 A JP S562662A JP 7820479 A JP7820479 A JP 7820479A JP 7820479 A JP7820479 A JP 7820479A JP S562662 A JPS562662 A JP S562662A
Authority
JP
Japan
Prior art keywords
region
circuit
wiring
regions
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7820479A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6230500B2 (enExample
Inventor
Akira Masaki
Tsuneyo Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7820479A priority Critical patent/JPS562662A/ja
Publication of JPS562662A publication Critical patent/JPS562662A/ja
Publication of JPS6230500B2 publication Critical patent/JPS6230500B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons

Landscapes

  • Semiconductor Integrated Circuits (AREA)
JP7820479A 1979-06-22 1979-06-22 Laminated electric circuit Granted JPS562662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7820479A JPS562662A (en) 1979-06-22 1979-06-22 Laminated electric circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7820479A JPS562662A (en) 1979-06-22 1979-06-22 Laminated electric circuit

Publications (2)

Publication Number Publication Date
JPS562662A true JPS562662A (en) 1981-01-12
JPS6230500B2 JPS6230500B2 (enExample) 1987-07-02

Family

ID=13655487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7820479A Granted JPS562662A (en) 1979-06-22 1979-06-22 Laminated electric circuit

Country Status (1)

Country Link
JP (1) JPS562662A (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61180468A (ja) * 1985-02-06 1986-08-13 Agency Of Ind Science & Technol 積層半導体装置
DE3623735A1 (de) * 1985-07-19 1987-01-22 Hitachi Ltd Signaluebertragungsschaltung
US4893174A (en) * 1985-07-08 1990-01-09 Hitachi, Ltd. High density integration of semiconductor circuit
US5165010A (en) * 1989-01-06 1992-11-17 Hitachi, Ltd. Information processing system
JP2005093999A (ja) * 2003-09-05 2005-04-07 Sun Microsyst Inc 電気的にアライメントされた向上した近接性通信
JP2005535116A (ja) * 2002-07-29 2005-11-17 サン・マイクロシステムズ・インコーポレイテッド 容量的結合チップパッドを電気的にアラインメントするための方法および装置
JP2008004714A (ja) * 2006-06-22 2008-01-10 Nec Corp チップ積層型半導体装置
US7990747B2 (en) 2007-03-09 2011-08-02 Nec Corporation Semiconductor chip and semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61180468A (ja) * 1985-02-06 1986-08-13 Agency Of Ind Science & Technol 積層半導体装置
US4893174A (en) * 1985-07-08 1990-01-09 Hitachi, Ltd. High density integration of semiconductor circuit
DE3623735A1 (de) * 1985-07-19 1987-01-22 Hitachi Ltd Signaluebertragungsschaltung
US4723082A (en) * 1985-07-19 1988-02-02 Hitachi, Ltd. Signal transfer circuit for use in laminated multilayer electric circuit
US5165010A (en) * 1989-01-06 1992-11-17 Hitachi, Ltd. Information processing system
JP2005535116A (ja) * 2002-07-29 2005-11-17 サン・マイクロシステムズ・インコーポレイテッド 容量的結合チップパッドを電気的にアラインメントするための方法および装置
JP2005093999A (ja) * 2003-09-05 2005-04-07 Sun Microsyst Inc 電気的にアライメントされた向上した近接性通信
JP2008004714A (ja) * 2006-06-22 2008-01-10 Nec Corp チップ積層型半導体装置
US7990747B2 (en) 2007-03-09 2011-08-02 Nec Corporation Semiconductor chip and semiconductor device

Also Published As

Publication number Publication date
JPS6230500B2 (enExample) 1987-07-02

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