JPS5622138A - Dynamic replacing system for microprogram - Google Patents

Dynamic replacing system for microprogram

Info

Publication number
JPS5622138A
JPS5622138A JP9759979A JP9759979A JPS5622138A JP S5622138 A JPS5622138 A JP S5622138A JP 9759979 A JP9759979 A JP 9759979A JP 9759979 A JP9759979 A JP 9759979A JP S5622138 A JPS5622138 A JP S5622138A
Authority
JP
Japan
Prior art keywords
address
region
register
written
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9759979A
Other languages
Japanese (ja)
Inventor
Hideyuki Saso
Ichiro Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9759979A priority Critical patent/JPS5622138A/en
Publication of JPS5622138A publication Critical patent/JPS5622138A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To attain an extremely high-speed execution even for the special data process, by providing the variable region to the memory device and then storing variably the microinstruction when necessary into the variable region.
CONSTITUTION: Variable region A is provided to memory device 1. When region A is used as the main memory part, the head address is expressed in the form of M0+X for the region exclusive for the main memory part, where M0 is the head address and X is the size of the address region each. Accordingly, the access is given to the main memory part with head address M0 used as the starting point. In other words, the 1st arithmetic circuit 2 is made through, and address M0 to be written into address 5 of the normal start point is written into MS head address register 6. And when the logical address of memory part MS to be given access to logic address register 7 is transmitted from other part, the operation is given to address M0 stored in register 6 and the logical address of part MS through the 2nd arithmetic circuit 3. Thus the real address of part MS is calculated to be written into output register 8.
COPYRIGHT: (C)1981,JPO&Japio
JP9759979A 1979-07-31 1979-07-31 Dynamic replacing system for microprogram Pending JPS5622138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9759979A JPS5622138A (en) 1979-07-31 1979-07-31 Dynamic replacing system for microprogram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9759979A JPS5622138A (en) 1979-07-31 1979-07-31 Dynamic replacing system for microprogram

Publications (1)

Publication Number Publication Date
JPS5622138A true JPS5622138A (en) 1981-03-02

Family

ID=14196692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9759979A Pending JPS5622138A (en) 1979-07-31 1979-07-31 Dynamic replacing system for microprogram

Country Status (1)

Country Link
JP (1) JPS5622138A (en)

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