JPS54117645A - Buffer memory control system - Google Patents
Buffer memory control systemInfo
- Publication number
- JPS54117645A JPS54117645A JP2465478A JP2465478A JPS54117645A JP S54117645 A JPS54117645 A JP S54117645A JP 2465478 A JP2465478 A JP 2465478A JP 2465478 A JP2465478 A JP 2465478A JP S54117645 A JPS54117645 A JP S54117645A
- Authority
- JP
- Japan
- Prior art keywords
- data block
- address
- buffer memory
- control part
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Computer And Data Communications (AREA)
Abstract
PURPOSE: To improve the use efficiency of a buffer memory by stopping immediately the transmission/receiving processing of a data block where a fault occurrs and making it possible to restart the transmission/receiving processing of the next data block.
CONSTITUTION: In case that line control part 202 detects anomaly occurrence in the receiving operation, the receiving operation of the block is stopped to restart to store the next data block from the next address. Meanwhile, in case that control part 202 detects anomaly occurrence in the transmission operation, executing address 303 is corrected to set the start address of the data block if one data block write completion indication 304 is set by interface control part 200; and executing addresses 302 and 303 are caused to agree with each other forcedly to set this address as the start address of the data block if the final address has not been set yet. As a result, the needless processing at an anomaly occurrence time is eliminated to be able to improve the use efficiency of the buffer memory.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2465478A JPS54117645A (en) | 1978-03-03 | 1978-03-03 | Buffer memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2465478A JPS54117645A (en) | 1978-03-03 | 1978-03-03 | Buffer memory control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54117645A true JPS54117645A (en) | 1979-09-12 |
JPS5719804B2 JPS5719804B2 (en) | 1982-04-24 |
Family
ID=12144120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2465478A Granted JPS54117645A (en) | 1978-03-03 | 1978-03-03 | Buffer memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54117645A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59165610U (en) * | 1983-04-21 | 1984-11-06 | 三菱電機株式会社 | fluorescent light |
-
1978
- 1978-03-03 JP JP2465478A patent/JPS54117645A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5719804B2 (en) | 1982-04-24 |
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