JPS5621404A - Am synchronous detecting circuit - Google Patents

Am synchronous detecting circuit

Info

Publication number
JPS5621404A
JPS5621404A JP9800979A JP9800979A JPS5621404A JP S5621404 A JPS5621404 A JP S5621404A JP 9800979 A JP9800979 A JP 9800979A JP 9800979 A JP9800979 A JP 9800979A JP S5621404 A JPS5621404 A JP S5621404A
Authority
JP
Japan
Prior art keywords
frequency
signal
input
output
frequency divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9800979A
Other languages
Japanese (ja)
Inventor
Akiji Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Tottori Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Tottori Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP9800979A priority Critical patent/JPS5621404A/en
Publication of JPS5621404A publication Critical patent/JPS5621404A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00Demodulation of amplitude-modulated oscillations
    • H03D1/22Homodyne or synchrodyne circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain a synchronous detector which does not require a phase shifter, by setting the oscillation frequency of the VCO of the PLL circuit, which is synchronized with an input signal, to the double of the input signal frequency and by frequency-dividing the output of the VCO by 1/2 at the rise and the fall of the oscillation frequency. CONSTITUTION:The oscillation frequency of VCO7 of PLL circuit 1 is set to 910 kHz which is the double of the input intermediate frequency signal, and frequency divider 8 is the 1/2 frequency divider operated by the rise and has the output applied to phase comparator 5. Frequency divider 9 is the 1/2 frequency divider operated at the fall and has the output applied to the second phase comparator 3, and the input inermediate frequency signal is detected synchronously, and the detection output is taken out through LPF4 to obtain a reproducing signal. Phase difference 90 deg. exists between outputs of frequency dividers 8 and 9.
JP9800979A 1979-07-31 1979-07-31 Am synchronous detecting circuit Pending JPS5621404A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9800979A JPS5621404A (en) 1979-07-31 1979-07-31 Am synchronous detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9800979A JPS5621404A (en) 1979-07-31 1979-07-31 Am synchronous detecting circuit

Publications (1)

Publication Number Publication Date
JPS5621404A true JPS5621404A (en) 1981-02-27

Family

ID=14207734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9800979A Pending JPS5621404A (en) 1979-07-31 1979-07-31 Am synchronous detecting circuit

Country Status (1)

Country Link
JP (1) JPS5621404A (en)

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