JPS5619640A - Ic carrier - Google Patents

Ic carrier

Info

Publication number
JPS5619640A
JPS5619640A JP8146980A JP8146980A JPS5619640A JP S5619640 A JPS5619640 A JP S5619640A JP 8146980 A JP8146980 A JP 8146980A JP 8146980 A JP8146980 A JP 8146980A JP S5619640 A JPS5619640 A JP S5619640A
Authority
JP
Japan
Prior art keywords
lead wires
carrier
package
contacting
contain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8146980A
Other languages
Japanese (ja)
Inventor
Yoshiaki Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8146980A priority Critical patent/JPS5619640A/en
Publication of JPS5619640A publication Critical patent/JPS5619640A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • H01L21/67396Closed carriers characterised by the presence of antistatic elements

Abstract

PURPOSE:To prevent the breakdown of an IC owing to its voltage at the time of transporting it and stocking it by forming the portion of contacting the lead wire of an IC package with the carrier conductive. CONSTITUTION:In order to contain lead wires led out horizontally from the IC package, ridge projections 6 are formed in parallel with the carrier body 5, and an opening 7 is perforated at the center to contain the package therein. Conductivity is imparted to the portion of contacting the body 5 with the lead wires through metal 4. This configuration can exactly retain the IC via the carrier 3, respective lead wires 1 are shorted with each other in contact with the metallic surfaces of the same size to produce no potential between the lead wires so that the IC is not broken by the static or surge voltage applied to the lead wires mounted on the carrier.
JP8146980A 1980-06-18 1980-06-18 Ic carrier Pending JPS5619640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8146980A JPS5619640A (en) 1980-06-18 1980-06-18 Ic carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8146980A JPS5619640A (en) 1980-06-18 1980-06-18 Ic carrier

Publications (1)

Publication Number Publication Date
JPS5619640A true JPS5619640A (en) 1981-02-24

Family

ID=13747256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8146980A Pending JPS5619640A (en) 1980-06-18 1980-06-18 Ic carrier

Country Status (1)

Country Link
JP (1) JPS5619640A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4319742Y1 (en) * 1965-10-23 1968-08-17

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4319742Y1 (en) * 1965-10-23 1968-08-17

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