JPS5617826B2 - - Google Patents

Info

Publication number
JPS5617826B2
JPS5617826B2 JP5979875A JP5979875A JPS5617826B2 JP S5617826 B2 JPS5617826 B2 JP S5617826B2 JP 5979875 A JP5979875 A JP 5979875A JP 5979875 A JP5979875 A JP 5979875A JP S5617826 B2 JPS5617826 B2 JP S5617826B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP5979875A
Other languages
Japanese (ja)
Other versions
JPS51282A (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS51282A publication Critical patent/JPS51282A/ja
Publication of JPS5617826B2 publication Critical patent/JPS5617826B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/0133Aspects related to lithography, isolation or planarisation of the conductor at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30Diffusion for doping of conductive or resistive layers
    • H10P32/302Doping polycrystalline silicon or amorphous silicon layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/60Wet etching
    • H10P50/66Wet etching of conductive or resistive materials
    • H10P50/663Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
JP5979875A 1974-05-21 1975-05-21 Expired JPS5617826B2 (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2258374A GB1477511A (en) 1974-05-21 1974-05-21 Methods of manufacturing semiconductor devices

Publications (2)

Publication Number Publication Date
JPS51282A JPS51282A (en:Method) 1976-01-05
JPS5617826B2 true JPS5617826B2 (en:Method) 1981-04-24

Family

ID=10181779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5979875A Expired JPS5617826B2 (en:Method) 1974-05-21 1975-05-21

Country Status (6)

Country Link
JP (1) JPS5617826B2 (en:Method)
CA (1) CA1040749A (en:Method)
DE (1) DE2522448A1 (en:Method)
FR (1) FR2272486B1 (en:Method)
GB (1) GB1477511A (en:Method)
NL (1) NL7505698A (en:Method)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit
JPS598855Y2 (ja) * 1978-09-01 1984-03-19 大阪電気株式会社 ワイヤ送給装置
JPS5546570A (en) * 1978-09-30 1980-04-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Method of fabricating mos semiconductor device
US4298402A (en) * 1980-02-04 1981-11-03 Fairchild Camera & Instrument Corp. Method of fabricating self-aligned lateral bipolar transistor utilizing special masking techniques
JPS6070401U (ja) * 1983-10-24 1985-05-18 株式会社月星製作所 車輪用スポ−ク
CN105824160B (zh) * 2015-01-08 2020-06-16 群创光电股份有限公司 显示面板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5542501B2 (en:Method) * 1974-01-29 1980-10-31

Also Published As

Publication number Publication date
GB1477511A (en) 1977-06-22
DE2522448A1 (de) 1975-12-04
JPS51282A (en:Method) 1976-01-05
FR2272486A1 (en:Method) 1975-12-19
FR2272486B1 (en:Method) 1979-01-19
CA1040749A (en) 1978-10-17
NL7505698A (nl) 1975-11-25

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