JPS5617458A - Parallel processing computer - Google Patents

Parallel processing computer

Info

Publication number
JPS5617458A
JPS5617458A JP9292779A JP9292779A JPS5617458A JP S5617458 A JPS5617458 A JP S5617458A JP 9292779 A JP9292779 A JP 9292779A JP 9292779 A JP9292779 A JP 9292779A JP S5617458 A JPS5617458 A JP S5617458A
Authority
JP
Japan
Prior art keywords
buffer memories
bus
fifo buffer
parallel processing
processing computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9292779A
Other languages
Japanese (ja)
Other versions
JPS6155706B2 (en
Inventor
Tatsuo Nogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP9292779A priority Critical patent/JPS5617458A/en
Publication of JPS5617458A publication Critical patent/JPS5617458A/en
Publication of JPS6155706B2 publication Critical patent/JPS6155706B2/ja
Granted legal-status Critical Current

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  • Complex Calculations (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To obtain an MIMD type multiple computer of high efficiency by using a linear array of processors and two-dimentional arrays of buffer memories.
CONSTITUTION: Master processor MU is connected to two-dimentionally arrayed FIFO buffer memories (i,j)[i and j are 0, 1...N-1], and slave processor AU-j is connected by bus to all of FIFO buffer memories on the j-th line. Every memory (i,j) is provided with a circulating data bus for return from its output side to its input side. The parallel computer with the bus building like this provides direct data transfer and interchange between MU and AU, and AUs, improves in versatility and efficiency, and is effective to matrix calculation or FET calculation.
COPYRIGHT: (C)1981,JPO&Japio
JP9292779A 1979-07-21 1979-07-21 Parallel processing computer Granted JPS5617458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9292779A JPS5617458A (en) 1979-07-21 1979-07-21 Parallel processing computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9292779A JPS5617458A (en) 1979-07-21 1979-07-21 Parallel processing computer

Publications (2)

Publication Number Publication Date
JPS5617458A true JPS5617458A (en) 1981-02-19
JPS6155706B2 JPS6155706B2 (en) 1986-11-28

Family

ID=14068120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9292779A Granted JPS5617458A (en) 1979-07-21 1979-07-21 Parallel processing computer

Country Status (1)

Country Link
JP (1) JPS5617458A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175174A (en) * 1984-02-21 1985-09-09 Agency Of Ind Science & Technol Parallel data transfer system
US5513364A (en) * 1993-03-09 1996-04-30 Matsushita Electric Industrial Co., Ltd. Data transfer device and multiprocessor system
FR2736726A1 (en) * 1989-12-28 1997-01-17 Thomson Csf Real time Detector/Locator System for RF Signals
US5751616A (en) * 1995-11-29 1998-05-12 Fujitsu Limited Memory-distributed parallel computer and method for fast fourier transformation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175174A (en) * 1984-02-21 1985-09-09 Agency Of Ind Science & Technol Parallel data transfer system
FR2736726A1 (en) * 1989-12-28 1997-01-17 Thomson Csf Real time Detector/Locator System for RF Signals
US5513364A (en) * 1993-03-09 1996-04-30 Matsushita Electric Industrial Co., Ltd. Data transfer device and multiprocessor system
US5751616A (en) * 1995-11-29 1998-05-12 Fujitsu Limited Memory-distributed parallel computer and method for fast fourier transformation

Also Published As

Publication number Publication date
JPS6155706B2 (en) 1986-11-28

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