JPS5616998A - Reproducing unit of transfer charge - Google Patents

Reproducing unit of transfer charge

Info

Publication number
JPS5616998A
JPS5616998A JP9125079A JP9125079A JPS5616998A JP S5616998 A JPS5616998 A JP S5616998A JP 9125079 A JP9125079 A JP 9125079A JP 9125079 A JP9125079 A JP 9125079A JP S5616998 A JPS5616998 A JP S5616998A
Authority
JP
Japan
Prior art keywords
bit
information
circuit
reproducing unit
transfer charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9125079A
Other languages
Japanese (ja)
Inventor
Hideo Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9125079A priority Critical patent/JPS5616998A/en
Publication of JPS5616998A publication Critical patent/JPS5616998A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make broad the operating margin of CCD, by changing the reference voltage and adding it to the reproduction circuit according to the information before by one bit.
CONSTITUTION: The charge transferred in the signal charge transfer regsiter 100 with the clocks ϕ3Wϕ1 fed to the electrodes 301W302 is converted into a voltage at the diffusion layer 305 and fed to the reproduction circuit 200. In this case, the gate ("1") circuit 300 and gate ("0") circuit 400 are operated according to ϕ1. Further, if the information in the bit before is at "1", the reference level to the next bit is at Vref ("1"), and if the information of the bit before is at "0", the reference level to the next bit is at Vref ("0"). As a result, broad operating margin can be obtained.
COPYRIGHT: (C)1981,JPO&Japio
JP9125079A 1979-07-18 1979-07-18 Reproducing unit of transfer charge Pending JPS5616998A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9125079A JPS5616998A (en) 1979-07-18 1979-07-18 Reproducing unit of transfer charge

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9125079A JPS5616998A (en) 1979-07-18 1979-07-18 Reproducing unit of transfer charge

Publications (1)

Publication Number Publication Date
JPS5616998A true JPS5616998A (en) 1981-02-18

Family

ID=14021165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9125079A Pending JPS5616998A (en) 1979-07-18 1979-07-18 Reproducing unit of transfer charge

Country Status (1)

Country Link
JP (1) JPS5616998A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860494A (en) * 1981-09-08 1983-04-09 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Binary information detection method and apparatus
JPH0264291U (en) * 1988-11-02 1990-05-15

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5860494A (en) * 1981-09-08 1983-04-09 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Binary information detection method and apparatus
JPH0264291U (en) * 1988-11-02 1990-05-15

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