JPS56168209A - Process input and output controller - Google Patents

Process input and output controller

Info

Publication number
JPS56168209A
JPS56168209A JP7144780A JP7144780A JPS56168209A JP S56168209 A JPS56168209 A JP S56168209A JP 7144780 A JP7144780 A JP 7144780A JP 7144780 A JP7144780 A JP 7144780A JP S56168209 A JPS56168209 A JP S56168209A
Authority
JP
Japan
Prior art keywords
process input
instruction
output
input
operation mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7144780A
Other languages
Japanese (ja)
Inventor
Masaki Nonaka
Katsuhiko Kakima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Facom Corp
Original Assignee
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Facom Corp filed Critical Fuji Facom Corp
Priority to JP7144780A priority Critical patent/JPS56168209A/en
Publication of JPS56168209A publication Critical patent/JPS56168209A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B15/00—Systems controlled by a computer
    • G05B15/02—Systems controlled by a computer electric

Abstract

PURPOSE:To easily execute a test while operating a process, by designating a process input/output instruction as a temporary operation mode at the time of a test, and writing an output in a memory area for debugging. CONSTITUTION:A microprocessor 6 executes its operation by decoding a process input/output instruction which is sent to a processor input/output device 3' through a connecting transmission line 5 from a computer 2, and giving an instruction to a process input/output device 4 through an interface 9. The process input/output instruction is provided with bits for designating a real operation mode and a temporary operation mode. When an instruction of said temporary operation mode has been given, if it is related to an input, the same operation as usual is executed. In the even of an output instruction, operation to the process input/output device is not executed, and writing to a debug memory 7 is executed.
JP7144780A 1980-05-30 1980-05-30 Process input and output controller Pending JPS56168209A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7144780A JPS56168209A (en) 1980-05-30 1980-05-30 Process input and output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7144780A JPS56168209A (en) 1980-05-30 1980-05-30 Process input and output controller

Publications (1)

Publication Number Publication Date
JPS56168209A true JPS56168209A (en) 1981-12-24

Family

ID=13460808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7144780A Pending JPS56168209A (en) 1980-05-30 1980-05-30 Process input and output controller

Country Status (1)

Country Link
JP (1) JPS56168209A (en)

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