JPS56166572A - Computer system composed of plural processors connected to multibit data buses - Google Patents

Computer system composed of plural processors connected to multibit data buses

Info

Publication number
JPS56166572A
JPS56166572A JP6072381A JP6072381A JPS56166572A JP S56166572 A JPS56166572 A JP S56166572A JP 6072381 A JP6072381 A JP 6072381A JP 6072381 A JP6072381 A JP 6072381A JP S56166572 A JPS56166572 A JP S56166572A
Authority
JP
Japan
Prior art keywords
computer system
data buses
system composed
processors connected
plural processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6072381A
Other languages
English (en)
Japanese (ja)
Inventor
Furiirinku Hendoriku
Uiremuse Adoriaan
Marinasu Arufuon Ma Edeyuarudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of JPS56166572A publication Critical patent/JPS56166572A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP6072381A 1980-04-23 1981-04-23 Computer system composed of plural processors connected to multibit data buses Pending JPS56166572A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8002344A NL8002344A (nl) 1980-04-23 1980-04-23 Multiprocessor systeem met gemeenschappelijke data/adres-bus.

Publications (1)

Publication Number Publication Date
JPS56166572A true JPS56166572A (en) 1981-12-21

Family

ID=19835184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6072381A Pending JPS56166572A (en) 1980-04-23 1981-04-23 Computer system composed of plural processors connected to multibit data buses

Country Status (5)

Country Link
JP (1) JPS56166572A (nl)
DE (1) DE3115454A1 (nl)
FR (1) FR2481488A1 (nl)
GB (1) GB2074764A (nl)
NL (1) NL8002344A (nl)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8005458A (nl) * 1980-10-02 1982-05-03 Philips Nv Kommunikatiesysteem en station geschikt hiervoor.
US4451881A (en) * 1981-11-03 1984-05-29 International Business Machines Corp. Data processing system bus for multiple independent users
FR2519165B1 (fr) * 1981-12-30 1987-01-16 Finger Ulrich Procede d'echange de donnees entre des modules de traitement et une memoire commune dans un systeme de traitement de donnees et dispositif pour la mise en oeuvre de ce procede
GB2125257B (en) * 1982-08-04 1986-03-26 Plessey Co Plc Improved local area network systems
GB8316463D0 (en) * 1983-06-16 1983-07-20 Secr Defence Priority resolution in bus oriented computer systems
GB2143349B (en) * 1983-06-16 1987-12-02 Secr Defence 'priority resolution in bus orientated computer system'
US4791562A (en) 1985-12-02 1988-12-13 Unisys Corporation Data processing system in which modules logically "OR" number sequences onto control lines to obtain the use of a time shared bus
JPH0697450B2 (ja) * 1987-10-30 1994-11-30 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン コンピユータ・システム
DE58908227D1 (de) * 1988-07-07 1994-09-29 Siemens Ag Schaltungsanordnung zur Prioritätsauswahl.
GB2230166A (en) * 1989-03-31 1990-10-10 Daniel Matthew Taub Resource control allocation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3710351A (en) * 1971-10-12 1973-01-09 Hitachi Ltd Data transmitting apparatus in information exchange system using common bus
JPS534761B2 (nl) * 1971-12-10 1978-02-21
DE2210426C2 (de) * 1972-03-03 1973-11-08 Nixdorf Computer Ag, 4790 Paderborn Verfahren zur vorranggesteuerten Auswahl einer von mehreren Funktions einheiten zur Anschaltung an eine ihnen gemeinsam zugeordnete Einrichtung in Datenverarbeitungsanlagen und Schaltung zur Durchführung des Verfahrens
GB1480208A (en) * 1974-07-03 1977-07-20 Data Loop Ltd Digital computers

Also Published As

Publication number Publication date
FR2481488A1 (fr) 1981-10-30
NL8002344A (nl) 1981-11-16
DE3115454A1 (de) 1982-04-08
GB2074764A (en) 1981-11-04

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