JPS56166529A - Control system for input and output device - Google Patents

Control system for input and output device

Info

Publication number
JPS56166529A
JPS56166529A JP6981580A JP6981580A JPS56166529A JP S56166529 A JPS56166529 A JP S56166529A JP 6981580 A JP6981580 A JP 6981580A JP 6981580 A JP6981580 A JP 6981580A JP S56166529 A JPS56166529 A JP S56166529A
Authority
JP
Japan
Prior art keywords
section
access
data amount
input
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6981580A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0131223B2 (enrdf_load_stackoverflow
Inventor
Atsuo Tamura
Kenji Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6981580A priority Critical patent/JPS56166529A/ja
Publication of JPS56166529A publication Critical patent/JPS56166529A/ja
Publication of JPH0131223B2 publication Critical patent/JPH0131223B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP6981580A 1980-05-26 1980-05-26 Control system for input and output device Granted JPS56166529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6981580A JPS56166529A (en) 1980-05-26 1980-05-26 Control system for input and output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6981580A JPS56166529A (en) 1980-05-26 1980-05-26 Control system for input and output device

Publications (2)

Publication Number Publication Date
JPS56166529A true JPS56166529A (en) 1981-12-21
JPH0131223B2 JPH0131223B2 (enrdf_load_stackoverflow) 1989-06-23

Family

ID=13413626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6981580A Granted JPS56166529A (en) 1980-05-26 1980-05-26 Control system for input and output device

Country Status (1)

Country Link
JP (1) JPS56166529A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101620582A (zh) * 2008-07-01 2010-01-06 三星电子株式会社 使用混合dma来处理高速数据的设备和方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101620582A (zh) * 2008-07-01 2010-01-06 三星电子株式会社 使用混合dma来处理高速数据的设备和方法
EP2141606A1 (en) * 2008-07-01 2010-01-06 Samsung Electronics Co., Ltd. Apparatus and method for processing high speed data using hybrid DMA
US8060667B2 (en) 2008-07-01 2011-11-15 Samsung Electronics Co., Ltd. Apparatus and method for processing high speed data using hybrid DMA

Also Published As

Publication number Publication date
JPH0131223B2 (enrdf_load_stackoverflow) 1989-06-23

Similar Documents

Publication Publication Date Title
EP0378423A3 (en) Dma controller
JPS57178523A (en) Terminal controller
JPS56166529A (en) Control system for input and output device
JPS5730170A (en) Buffer memory control system
JPS6437640A (en) Control system for cache memory
JPS5495133A (en) Input/output processing control system
EP0120975A4 (en) DIGITAL CONTROL DEVICE AND METHOD.
JPS57205885A (en) Channel buffer controlling system
JPS54161855A (en) Input/output control system
JPS5798025A (en) Channel controller
JPS5674738A (en) Transfer system of display data
JPS57209525A (en) Access controlling system for channel buffer
JPS5393743A (en) Collective arithmetic unit
JPS5499882A (en) Plant supervisory controller
JPS52130260A (en) Data processing unit
JPS643706A (en) Controller
JPS57182841A (en) Sum system retrieval mechanism
JPS55119729A (en) Data processor
JPS5437443A (en) Computer interrution control system
JPS5769330A (en) Input/output control system
JPS5797175A (en) Data collection system
JPS52140784A (en) Sequence controller
JPS5730169A (en) Cash memory control system
JPS6466764A (en) Adaptor control system
JPS54114135A (en) Program loading system