JPS56163598A - Memory device - Google Patents

Memory device

Info

Publication number
JPS56163598A
JPS56163598A JP6588380A JP6588380A JPS56163598A JP S56163598 A JPS56163598 A JP S56163598A JP 6588380 A JP6588380 A JP 6588380A JP 6588380 A JP6588380 A JP 6588380A JP S56163598 A JPS56163598 A JP S56163598A
Authority
JP
Japan
Prior art keywords
cpu1
sent
rom
information
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6588380A
Other languages
Japanese (ja)
Inventor
Keizou Naraba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6588380A priority Critical patent/JPS56163598A/en
Publication of JPS56163598A publication Critical patent/JPS56163598A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To eliminate a special parity check, by reading the memory information of an ROM by the write signal sent from a CPU and then giving a collation to the information. CONSTITUTION:The specific memory address of ROM elements 21 and 22 are selected by the address signal sent from a CPU1. The memory information of the selected address is sent to a register 3 by the write signal B sent from the CPU1. The information to be collated with the memory information of an ROM element is sent to a register 4 from the CPU1 simultaneously with an output of the signal B from the CPU1. The contents of registers 3 and 4 are compared to each other at a comparator 5. Then an interruption is applied to the CPU1 when no coincidence is obtained. The CPU1 sends the write signal to the ROM element to send the memory information of the ROM element to a register. Thus an efficient application is ensured for an instruction of the CPU.
JP6588380A 1980-05-20 1980-05-20 Memory device Pending JPS56163598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6588380A JPS56163598A (en) 1980-05-20 1980-05-20 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6588380A JPS56163598A (en) 1980-05-20 1980-05-20 Memory device

Publications (1)

Publication Number Publication Date
JPS56163598A true JPS56163598A (en) 1981-12-16

Family

ID=13299815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6588380A Pending JPS56163598A (en) 1980-05-20 1980-05-20 Memory device

Country Status (1)

Country Link
JP (1) JPS56163598A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5870493A (en) * 1981-09-30 1983-04-26 アドバンスト　マイクロ　デバイシス，インコーポレイテッド High speed prom device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5870493A (en) * 1981-09-30 1983-04-26 アドバンスト　マイクロ　デバイシス，インコーポレイテッド High speed prom device
JPH0324000B2 (en) * 1981-09-30 1991-04-02 Advanced Micro Devices Inc

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