JPS56157128A - Signal converter - Google Patents

Signal converter

Info

Publication number
JPS56157128A
JPS56157128A JP5945880A JP5945880A JPS56157128A JP S56157128 A JPS56157128 A JP S56157128A JP 5945880 A JP5945880 A JP 5945880A JP 5945880 A JP5945880 A JP 5945880A JP S56157128 A JPS56157128 A JP S56157128A
Authority
JP
Japan
Prior art keywords
terminals
signal
memory
memory output
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5945880A
Other languages
Japanese (ja)
Inventor
Tadao Totsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP5945880A priority Critical patent/JPS56157128A/en
Publication of JPS56157128A publication Critical patent/JPS56157128A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE:To deliver an input signal after converting it into a signal having a desired characteristics, by selecting properly the way of feedback of a memory output signal and the contents of storage. CONSTITUTION:A memory element M consisting of a decoder part DEC and a memory part MEM has the 4-bit address input signal terminals A1, A2, A4 and A8 plus the 3-bit memory output signal terminals D0, D1 and D2. These address input signal terminals are weighted to 2<0>, 2<1>, 2<2> and 2<3>, respectively; while the memory output signal terminals are weighted to 2<0>, 2<1> and 2<2>, respectively. Then a clock signal CK is applied to the terminal A1, and the memory output signals sent from the terminals D0, D1 and D2 are fed back to the terminals A2, A4 and A8 respectively in the form of the feedback address signals F.ADR. The storage contents of addresses 0-15 of the part MEM are selectively set properly in order to make function a signal converter consisting of a memory element M as an 8-notation counter of the clock signal CK.
JP5945880A 1980-05-07 1980-05-07 Signal converter Pending JPS56157128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5945880A JPS56157128A (en) 1980-05-07 1980-05-07 Signal converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5945880A JPS56157128A (en) 1980-05-07 1980-05-07 Signal converter

Publications (1)

Publication Number Publication Date
JPS56157128A true JPS56157128A (en) 1981-12-04

Family

ID=13113876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5945880A Pending JPS56157128A (en) 1980-05-07 1980-05-07 Signal converter

Country Status (1)

Country Link
JP (1) JPS56157128A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5479530A (en) * 1977-12-07 1979-06-25 Nec Corp Code converter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5479530A (en) * 1977-12-07 1979-06-25 Nec Corp Code converter

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