JPS56156048A - Data exchanging system - Google Patents

Data exchanging system

Info

Publication number
JPS56156048A
JPS56156048A JP5913180A JP5913180A JPS56156048A JP S56156048 A JPS56156048 A JP S56156048A JP 5913180 A JP5913180 A JP 5913180A JP 5913180 A JP5913180 A JP 5913180A JP S56156048 A JPS56156048 A JP S56156048A
Authority
JP
Japan
Prior art keywords
data
17frm
circuit
inhibits
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5913180A
Other languages
Japanese (ja)
Inventor
Senzo Sakasai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5913180A priority Critical patent/JPS56156048A/en
Publication of JPS56156048A publication Critical patent/JPS56156048A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/50Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H04L12/52Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
    • H04L12/525Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques involving a stored program control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To cope with various different speeds of transmission in an octet time- division multiplex system, by adding a timing control circuit and a bit control circuit. CONSTITUTION:A circuit that inhibits an FRM is provided by adding a circuit which inhibits the 17FRM by means of an n-bit shift register NBITSR and a decoder DECODE. Then the data is stored in the BUFF as if the data were given to a data buffer even during the 17FRM, and thus an amount equivalent to the 17FRM can be supplemented. In such a way, the data is received from a data highway with an even interval.
JP5913180A 1980-05-02 1980-05-02 Data exchanging system Pending JPS56156048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5913180A JPS56156048A (en) 1980-05-02 1980-05-02 Data exchanging system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5913180A JPS56156048A (en) 1980-05-02 1980-05-02 Data exchanging system

Publications (1)

Publication Number Publication Date
JPS56156048A true JPS56156048A (en) 1981-12-02

Family

ID=13104442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5913180A Pending JPS56156048A (en) 1980-05-02 1980-05-02 Data exchanging system

Country Status (1)

Country Link
JP (1) JPS56156048A (en)

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