JPS5773550A - Time division data exchange multiplex communcation control system - Google Patents
Time division data exchange multiplex communcation control systemInfo
- Publication number
- JPS5773550A JPS5773550A JP15037480A JP15037480A JPS5773550A JP S5773550 A JPS5773550 A JP S5773550A JP 15037480 A JP15037480 A JP 15037480A JP 15037480 A JP15037480 A JP 15037480A JP S5773550 A JPS5773550 A JP S5773550A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- reception
- signal transmission
- communcation
- control system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/16—Arrangements for providing special services to substations
- H04L12/18—Arrangements for providing special services to substations for broadcast or conference, e.g. multicast
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PURPOSE:To transmit the same transmission message to a plurality of lines simply, by providing an information bit which indicates whether the memory storing the intermediate information for transmission/reception is to be rewritten or not, with a signal transmission/reception control memory. CONSTITUTION:A signal transmission/reception control memory 11 is provided with an information bit 11c which indicates whether a memory 12 storing the intermediate information for transmission/reception is to be rewritten or not. To execute multiplex communication function to the signal transmission/reception control memory 11, the same number is written in a signal transmission/reception set number 11a of the memory 11 so that the same signal transmission/reception section can be connected to N lines and the rewrite of the memory 12 for the N lines can be made only once.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15037480A JPS5773550A (en) | 1980-10-27 | 1980-10-27 | Time division data exchange multiplex communcation control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15037480A JPS5773550A (en) | 1980-10-27 | 1980-10-27 | Time division data exchange multiplex communcation control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5773550A true JPS5773550A (en) | 1982-05-08 |
Family
ID=15495588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15037480A Pending JPS5773550A (en) | 1980-10-27 | 1980-10-27 | Time division data exchange multiplex communcation control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5773550A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6130155A (en) * | 1984-07-20 | 1986-02-12 | Fujitsu Ltd | Centralized supervisory system |
JPS6394742A (en) * | 1986-10-09 | 1988-04-25 | Nec Corp | Packet communication system |
-
1980
- 1980-10-27 JP JP15037480A patent/JPS5773550A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6130155A (en) * | 1984-07-20 | 1986-02-12 | Fujitsu Ltd | Centralized supervisory system |
JPH0332942B2 (en) * | 1984-07-20 | 1991-05-15 | Fujitsu Ltd | |
JPS6394742A (en) * | 1986-10-09 | 1988-04-25 | Nec Corp | Packet communication system |
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