JPS56154887A - Sampling circuit for video signal - Google Patents
Sampling circuit for video signalInfo
- Publication number
- JPS56154887A JPS56154887A JP5747080A JP5747080A JPS56154887A JP S56154887 A JPS56154887 A JP S56154887A JP 5747080 A JP5747080 A JP 5747080A JP 5747080 A JP5747080 A JP 5747080A JP S56154887 A JPS56154887 A JP S56154887A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- supplied
- data
- counter
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/025—Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
- H04N7/035—Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimiles In General (AREA)
- Television Systems (AREA)
Abstract
PURPOSE:To supply a sampling command at any time in one vertical scanning period, by providing a counter which outputs an address signal and a circuit which supplies a video signal corresponding to an optional picture-element position. CONSTITUTION:Counter 2 is reset with vertical synchronizing pulse VSYNC and then counts horizontal synchronizing signal pulses HSYNC successively. Its count value is supplied as address signal A to data buffer BF. Therefore, when timing signal TM is outputted from preset counter 11 at the timing that corresponds to a picture-element position specified with signal HP in each horizontal scanning period, video signal VD is fetched into shift register 12 by signal TM. Then, it is supplied as data SD to buffer BF. Consequently, data SD is stored successively in memory areas of the data buffer specified with signal A. Thus, the sampling start command is supplied at the same period as one vertical scanning time at a maximum.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5747080A JPS56154887A (en) | 1980-04-30 | 1980-04-30 | Sampling circuit for video signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5747080A JPS56154887A (en) | 1980-04-30 | 1980-04-30 | Sampling circuit for video signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56154887A true JPS56154887A (en) | 1981-11-30 |
Family
ID=13056574
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5747080A Pending JPS56154887A (en) | 1980-04-30 | 1980-04-30 | Sampling circuit for video signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56154887A (en) |
-
1980
- 1980-04-30 JP JP5747080A patent/JPS56154887A/en active Pending
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