JPS56153884A - Vertical reference pulse generation circuit - Google Patents
Vertical reference pulse generation circuitInfo
- Publication number
- JPS56153884A JPS56153884A JP5650080A JP5650080A JPS56153884A JP S56153884 A JPS56153884 A JP S56153884A JP 5650080 A JP5650080 A JP 5650080A JP 5650080 A JP5650080 A JP 5650080A JP S56153884 A JPS56153884 A JP S56153884A
- Authority
- JP
- Japan
- Prior art keywords
- output
- pulse
- circuit
- signal
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
Abstract
PURPOSE:To obtain a vertical reference pulse synchronized with a regular vertical synchronizing pulse when transmission distortion is generated in the TV signal due to noise, ghost, etc., by using a color burst signal to obtain the vertical reference pulse. CONSTITUTION:The video signal from input terminal 11 is applied to burst sampling pulse generating circuit 12, and the sampling pulse is applied to phase detector 13, and color burst signal Sb sampled from the signal is output to the output of detector 13. This signal Sb is applied to not only VCO15 of the PLL circuit constitution but also demodulating circuit 14 through phase shifter 18. The output of the PLL cicuits is applied to l frequency divider 17 to generate a clock which is synchronized with the horizontal synchronizing pulse and has a frequency twise as high as the horizontal scanning frequency, and this clock is applied to AND circuit 21 which gates the output of RSFF20, and the output of circuit 21 is applied to 525 frequency divider 32. The logical operation circuit to which the output of RSFF25 is input is controlled by the 512 frequency division output and the 513 frequency division output of frequency divider 22, thereby outputting a vertical reference pulse synchronized with the vertical pulse without using the vertical synchronizing pulse.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5650080A JPS5936470B2 (en) | 1980-04-28 | 1980-04-28 | Vertical reference pulse generation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5650080A JPS5936470B2 (en) | 1980-04-28 | 1980-04-28 | Vertical reference pulse generation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56153884A true JPS56153884A (en) | 1981-11-28 |
JPS5936470B2 JPS5936470B2 (en) | 1984-09-04 |
Family
ID=13028820
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5650080A Expired JPS5936470B2 (en) | 1980-04-28 | 1980-04-28 | Vertical reference pulse generation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5936470B2 (en) |
-
1980
- 1980-04-28 JP JP5650080A patent/JPS5936470B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5936470B2 (en) | 1984-09-04 |
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