JPS56147242A - Data control device - Google Patents

Data control device

Info

Publication number
JPS56147242A
JPS56147242A JP5085380A JP5085380A JPS56147242A JP S56147242 A JPS56147242 A JP S56147242A JP 5085380 A JP5085380 A JP 5085380A JP 5085380 A JP5085380 A JP 5085380A JP S56147242 A JPS56147242 A JP S56147242A
Authority
JP
Japan
Prior art keywords
level
instruction
instructions
register
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5085380A
Other languages
Japanese (ja)
Inventor
Kazutoshi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5085380A priority Critical patent/JPS56147242A/en
Publication of JPS56147242A publication Critical patent/JPS56147242A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To simplify development of the program and simplify the data processing device, by providing an identification in each instruction to make it possible that upper-level and lower-level instructions are mixed in the same memory device. CONSTITUTION:Machine language 11 as upper-level instructions and micro instructions 21 as lower-level instructions stored in main memory device 4 are accessed by memory address register 1; and if identification code 10 added to each instruction indicates the upper level, the instruction is read to memory data register 2; and if identification code 10 indicates the lower level, the instruction is read by intermediate register 5, and they are processed respectively. Since the machine language and micro instructions are mixed in the same memory device in this manner, the register group where data is stored is handled directly by various programs.
JP5085380A 1980-04-17 1980-04-17 Data control device Pending JPS56147242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5085380A JPS56147242A (en) 1980-04-17 1980-04-17 Data control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5085380A JPS56147242A (en) 1980-04-17 1980-04-17 Data control device

Publications (1)

Publication Number Publication Date
JPS56147242A true JPS56147242A (en) 1981-11-16

Family

ID=12870272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5085380A Pending JPS56147242A (en) 1980-04-17 1980-04-17 Data control device

Country Status (1)

Country Link
JP (1) JPS56147242A (en)

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